Actel Continues to Ease Embedded Design With Extensive Library of IP

Actel's IP Library Includes Support for the New SmartFusion Intelligent Mixed Signal FPGA

MOUNTAIN VIEW, Calif., May 11 — (PRNewswire) — Actel Corporation (Nasdaq: ACTL) today announced that embedded designers can now take advantage of a broad portfolio of Actel intellectual property (IP) cores available for SmartFusion™ intelligent mixed signal FPGAs. SmartFusion mixed signal FPGAs are the only device that combines an FPGA, ARM® Cortex™-M3 processor and programmable analog on a single chip. In addition to the multiple peripherals hard coded into the device, Actel enables full customization by offering an extensive library of soft peripherals that can be placed in the low power flash FPGA fabric.  

Actel's IP cores enable customers to easily incorporate robust functionality, take complete advantage of the newly introduced SmartFusion devices and build a solution that meets the exact needs of their design.

A large library of Actel IP cores are included in the Libero® Integrated Design Environment (IDE) IP bundle, with obfuscated-RTL version included with the FREE Libero Gold license, and RTL-source version included with the $2,500 Libero Platinum license. The library of Actel's IP cores can be configured and connected in the Libero IDE SmartDesign IP design tool.  

SmartFusion compatible Actel IP cores available in the Libero IDE SmartDesign IP design tool include:


Core16550

UART with or without FIFO software compatible with the Texas Instruments 16550 devices

Core3DES

Implements triple DES to NIST FIPS PUB 46-3 supporting 168-bit key size

Core429

Implements ARINC 429 two-wire, point-to-point serial control communications avionics data bus

Core8051s

ASM51-compatible 8051 microcontroller core with advanced peripheral bus (APB) bus

CoreABC

Simple low gate count controller for APB devices

CoreAES128

Implements the Advanced Encryption Standard (AES) using the Rijndael algorithm per FIPS PUB 197

CoreAHB

AMBA bus interface used to connect subsystem cores to Actel's 32-bit ARM processors

CoreAHB2APB

AHB slave that connects the AHB to the APB and acts as the master on the APB

CoreAHBLite

Multi-master implementation of AHB-Lite bus interconnect  standard used to connect subsystem cores to Actel's 32-bit ARM processors

CoreAhbSram

AHB bus interface to embedded SRAM memory blocks

CoreAHBtoAPB3

AHB slave and AMBA 3 APB master bridging between high-speed AHB domain and low-power APB domain

CoreAPB

AMBA bus interface used to connect subsystem cores to Actel's soft processors

CoreAPB3

AMBA bus interface used to connect subsystem cores to Actel's soft processors; fully compatible with the APB v3.0 protocol

CoreAPBSRAM

APB bus interface to embedded SRAM memory blocks

CoreCORDIC

CORDIC engine providing an iterative method of performing vector rotations using only shifts and adds

CoreDES

Implements DES to NIST FIPS PUB 46-3 supporting 56-bit key size

CoreEDAC

Error detection and correction (EDAC)

CoreFROM

APB slave that for access to SmartFusion 128-byte FlashROM  (FROM) memory

CoreGPIO

APB bus peripheral that provides up to 32 inputs and 32 outputs for general purpose use

CoreI2C

APB-driven serial interface, supporting I2C, SMBus, and PMBus data transfers

CoreInterrupt

APB Slave component that provides configurable interrupt processing

CoreLPC

Low-pin-count (LPC) APB component that accepts LPC host-side system interface commands

CoreMBX

Allows data messages (mail) to pass back and forth from one processing element to another via "mailbox" message handling scheme

CoreMemCtrl

AHB slave component that supports access to external SRAM and flash memory resources

CorePWM

General purpose multi-channel pulse width modulator (PWM) core for up to 16 separate PWM digital outputs, configurable via register values

CoreQEI

Quadrature Encoder core for motor control applications

CoreRemap

APB slave that is a small control block with a single bit register for control aliasing of memory resources at the bottom of the processor address space

CoreRSDEC

Configurable Actel FPGA–optimized Reed-Solomon decoder core RTL generator

CoreRSENC

Configurable Actel FPGA–optimized Reed-Solomon encoder core RTL generator

CoreSDR

Interface to external RAM supporting up to 1024 Mbytes via synchronous interface; supports all standard SDRAM chips and DIMMs

CoreSPI

Serial Peripheral Interface, master and/or slave, full duplex, synchronous, 8-bit serial data transfer, high bit rates

CoreTimer

APB slave that provides an interrupt-generating, programmable decrementing counter

CoreUART

Serial communication controller with a flexible serial data interface

CoreUARTapb

Serial communications interface with AMBA APB bus interface

CoreWatchdog

APB slave providing a means of monitoring processors for and recovering from software crashes





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