EDA Vendors Jointly Develop Extensions to Liberty Format for Current-Based Cell Models (ECSM)
SAN JOSE, Calif.--(BUSINESS WIRE)--June 18, 2003-- Cadence Design Systems Inc. and Silicon Metrics today announced development of nanometer-ready delay models based on extensions to the Liberty(tm) model format. The effective current source models (ECSM) can be created by Silicon Metrics' SiliconSmart(tm) library characterization tool and used by Cadence's nanometer delay calculator SignalStorm(tm), the common delay calculation engine of the Cadence(R) Encounter(tm) platform. This announcement is the result of close cooperation between the two companies in establishing the characterization requirements, model format definitions, and model qualification.
ECSM models have been shown in customer tests to provide superior
accuracy, often within 2% of SPICE models, and are particularly well
suited to modeling the voltage (IR) drop impact on delay that has a
major influence on timing at 180 nanometers and below. When used by
SignalStorm in conjunction with VoltageStorm(tm) IR drop analysis and
CeltIC(tm) crosstalk analysis, ECSM models provide the cornerstone of
Cadence's electrical signoff flow.
Until now, creating ECSM models required a separate timing
characterization process and a binary format. By extending the Liberty
format, Cadence and Silicon Metrics have unified timing
characterization into a single step and a single format that can
support both table lookup models and the advanced ECSM models.
Customers can now utilize the power of ECSM models while maintaining a
consistent set of timing views. Furthermore, tools that do not support
ECSM models will be able to read and ignore the ECSM extensions
without requiring any upgrades.
"As the industry transitions to finer process technologies, the
complexities of design and the requirement for delay analysis are
increasing dramatically," said Vess Johnson, president and CEO of
Silicon Metrics. "Successful design teams have recognized that the
accuracy of the characterization and models used during timing
analysis have a direct impact on the quality of their design, the
number of design iterations, and time to market."
"The accuracy of any analysis tool is only as good as the quality
of the models they consume; therefore, a key component of the design
team's success in performing nanometer signoff is the availability of
accurate delay models," said Ping Chao, senior vice president and
general manager, Chip Implementation at Cadence. "By providing
SPICE-qualified ECSM models, Silicon Metrics' SiliconSmart
characterization and modeling technology becomes an integral part of
the Cadence design flow."
About Cadence Design Systems
Cadence is the world's leader in electronic design technologies,
methodology services, and design services. Cadence solutions are used
to accelerate and manage the design of semiconductors, computer
systems, networking and telecommunications equipment, consumer
electronics, and a variety of other electronics-based products. With
approximately 5,200 employees and 2002 revenues of approximately $1.3
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and traded on the New York Stock Exchange under the symbol
CDN. More information about the company, its products and services is
About Silicon Metrics Corporation
Silicon Metrics' characterization and modeling products allow
customers to shorten design cycles and improve chip performance by
creating best-in-class models that combine silicon predictability with
designer productivity. Silicon Metrics has offices in Austin, Texas,
and San Jose, California. Silicon Metrics is represented by Advinno in
Singapore and Malaysia, Maojet in Taiwan, Marubeni Solutions in Japan,
MM Solutions in Europe and Israel, NewPlus in China, and Tritech
Systems in Korea. Company investors include Austin Ventures, Needham
Capital Partners, Current Ventures, and Cadence Design Systems Inc.
(NYSE:CDN). For more information, visit Silicon Metrics online at
Silicon Metrics, SiliconSmart , and the Silicon Metrics logo are
trademarks or registered trademarks of Silicon Metrics Corporation.
Cadence and the Cadence logo are registered trademark and SignalStorm,
VoltageStorm, Encounter and CeltIC are trademarks of Cadence Design
Systems Inc. All other company or product names are the registered
trademarks or trademarks of their respective owners.
CONTACT: Silicon Metrics Corporation Karen Caropepe, 512/651-1461 Email Contact or Cadence Design Systems Inc. Dean Solov, 408/914-6077 Email Contact