Adding Advanced Traffic Profile Generation to ESL Model Verification Solution
SANTA CLARA, Calif. — (BUSINESS WIRE) — February 24, 2010 — JEDA Technologies, the ESL model validation automation provider announces the availability of Intelligent Traffic-profile Generator (ITG), a dynamic traffic profile generator as an addition to the ESL model verification solution. For advanced multi-core designs, ITG addresses the need for early architecture exploration when software or a particular device model is not available yet.
ITG generates application- and architecture-specific transaction level traffic. In contrast to commonly used traffic generators, JEDA ITG provides dynamic reactivity to system feedback, such as interrupts, configuration interfaces or system status information. This means that the generated traffic profiles are simulating the transaction and system behavior more realistically. ITG is SystemC based and supports transaction level interfaces such as TLM2.0 LT and AT, OCP-TL1 and AXI as well as user defined interfaces.
ITG comes with traffic templates mimicking targeted devices such as CPU traffic at the output of their L1 or L2 instruction and data caches, video traffic as well as DMA specific traffic profiles. ITG templates can be calibrated with various parameters, like bandwidth, frequency or mega instructions per second (MIPS), to adjust the behavior to a specific hardware platform. Typically they are used to simulate the impact of traffic from one device to another in terms of throughput and latency when resources like interconnects and memory are shared.
"Increasingly, developers are relying on traffic profile generators and SystemC models for early system analysis and to extract the full performance of complex SoC designs," said Frank Ferro, director of marketing at Sonics. "With JEDA's intelligent traffic generation modeling and Sonics' SystemC models we give SoC designers a powerful, precision design environment to fully optimize the performance of Sonics' on-chip networks."
"We are providing a commercial solution with our differentiating traffic generator technology so that architects can obtain system exploration results much earlier," says Dr. Andrea Kroll, VP Marketing, JEDA Technologies. "JEDA ITG not only addresses certain master and slave model availability issues, but also enable system architects to explore architectures without waiting for running software."
JEDA ITG is available for Windows and Linux. Please contact Email Contact for more information. Also have a look at Webinar “System Optimization Techniques for Peak SoC Performance” at http://www.techonline.com/learning/webinar/219401399.
About JEDA Technologies
JEDA Technologies enables its customers to accelerate high level model development effort to reduce ESL design risks. We provide products and solutions to measure model quality, help manage ESL design and modeling project schedules. The solution includes advanced coverage tools for C++ and SystemC models as well as checkers for OCP and TLM-2.0-base SystemC models to automate self-checking and detect interoperability issues. The company was founded in 2002 in Santa Clara, California. For more information, please visit www.jedatechnologies.net.
Andrea Kroll, 408-912-1856