Synopsys Chosen as Primary EDA Partner by Hisilicon

MOUNTAIN VIEW, Calif., Dec. 7 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Hisilicon Technologies Co., Ltd., a worldwide provider of ASICs and solutions for communication network and digital media, and a subsidiary of Huawei Technologies, has established Synopsys as its primary EDA partner across its implementation and verification design flows. Hisilicon has signed an expanded business agreement to extend its use of Synopsys' IC Compiler place-and-route technology and DesignWare(R) IP as well as other tools from the broad spectrum of Synopsys' Galaxy(TM) Implementation and Discovery(TM) Verification Platforms.

"Since its founding, Hisilicon has carefully selected the key strategic partnerships that help us deliver high quality ICs and services to our customers," said Teresa He, vice president of Hisilicon Technologies Co., Ltd. "We chose to partner with Synopsys because of their technology and proven ability to help make us successful. By helping us deploy advanced technologies such as the VMM verification methodology and advanced chip synthesis to improve design and verification productivity, Synopsys has reinforced our confidence in its short- and long-term technical leadership."

"Within a relatively short period of time, Hisilicon has established itself as one of the premier fabless IC design companies in China, and we are grateful to play a supporting role in their success," said John Chilton, senior vice president of marketing and strategic development at Synopsys. "By increasing their usage of Synopsys tools, IP and services, Hisilicon will be able to continue to aggressively focus on bringing differentiated network communications and digital media silicon solutions to market."

With this expanded agreement, Hisilicon has broad access to tools and IP from Synopsys, including the Galaxy Implementation Platform's IC Compiler place-and-route technology, DC Ultra(R) RTL synthesis, DFTMAX(TM) compression, Formality(R) power-aware equivalence checking, PrimeTime(R) SI signal integrity analysis, PrimeTime PX power analysis and StarRC(TM) parasitic extraction; the Discovery Verification Platform's VCS(R) with MVSIM voltage-aware simulator and HSPICE circuit simulator, and MVRC voltage-aware static rule checker; System Studio algorithm design and analysis; and DesignWare(R) IP for PCI Express 2.0, SuperSpeed USB 3.0 and DDR2/3.

About Synopsys

Synopsys, Inc. (NASDAQ: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Synopsys, DC Ultra, DFT MAX, DesignWare, Discovery, Formality, Galaxy, HSPICE, PrimeTime, StarRC, and VCS are trademarks or registered trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.


Editorial Contact:
Yvette Huygen
Synopsys, Inc.
650-584-4547
yvetteh@synopsys.com

Investor Contact:
Lisa Ewbank
Synopsys, Inc.
650-584-1901

Web site: http://www.synopsys.com/




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