Verific Design Automation Tools Deliver Industry-Leading RTL Language Support for Xilinx ISE Design Suite

ALAMEDA, Calif. — (BUSINESS WIRE) — June 24, 2009 Verific Design Automation ( www.verific.com) today announced that its register transfer level (RTL) front ends have been licensed by Xilinx ( www.xilinx.com) for the latest version of ISE® Design Suite, equipping Xilinx customers with robust RTL language support for the new Virtex 6 and Spartan 6 FPGAs.

Xilinx has integrated Verific’s de facto standard Verilog and VHDL parsers, analyzers and elaborators to provide a common, proven and reliable RTL front end for its synthesis, simulation and design entry products. ISE Design Suite 11, the latest release of the industry-leading environment for FPGA design, delivers a new generation of complete, domain-specific development environments for logic design, DSP design, embedded design and complete system level design.

“Verific has been an exceptional technology partner with a team whose expertise we value,” notes Dan Gibbons, Xilinx’s senior director for Interactive Design Tools. “Verific has delivered high-quality RTL front-end software to help us differentiate ISE Design Suite’s superior capabilities and benefits and allow us to focus on our core competencies.”

Verific’s software serves as the front end to electronic design automation (EDA) and FPGA tools such as Xilinx’s ISE Design Suite to analyze, verify, synthesize and modify designs for the past 10 years. Its products are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and comes with support and maintenance.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, is a leading provider of SystemVerilog, Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.



Contact:

Public Relations for Verific
Nanette Collins, 617-437-1822
Email Contact




Review Article Be the first to review this article
Rand3D

IMTS 2018 Register Now>>

Featured Video
Jobs
Mechanical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Mid-Level Mechanical Engineer for Kiewit at lenexa, Kansas
Upcoming Events
Inside 3D Printing Seoul 2018 at Korea International Exhibition Center (KINTEX), Hall 5 408 Hallyuworld-ro, Ilsanseo-gu, Goyang-si, Gyeonggi-do Goyang Korea (South) - Jun 27 - 29, 2018
AMTEX 2018 at Pragati Maidan New Delhi India - Jul 6 - 9, 2018
34th Annual Coordinate Metrology Society Conference 2018 at Grand Sierra Resort, 2500 East Second Street Meeting & Covention Center Reno NV - Jul 23 - 27, 2018
Kenesto: 30 day trial
SolidCAM: Break the Chains



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise