Developed by Taray, Inc. and available to Cadence customers through an OEM agreement, this exclusive joint solution offers an optimized correct-by-construction FPGA pin assignment that reduces the number of pin optimization iterations during PCB layout while reducing the number of layers required to route the FPGA on a PCB design. Allegro FPGA System Planner also shortens time for companies using FPGAs on PCB systems to emulate their ASICs through automated FPGA pin assignment.
"I tried other tools that promised to simplify the FPGA I/O complexity issue but none of these had an approach like Taray does," said Roberto Cordero, GCSD Signal Integrity TMT Lead of Harris Corporation. "Taray's FPGA I/O synthesis technology is the only one that allows us to enter our design intent at the system level, and then it completely automates the pin assignment over multiple FPGAs all at once. The Taray technology will be a very strong addition to Cadence's portfolio."
The need among systems companies for increased data throughput along with increased functionality in their products has resulted in large pin-count FPGAs with high-speed I/Os. These FPGAs also have more advanced memory interfaces that consume much less power and address customers' desire to develop greener products. Use of such FPGAs with greater capacity, more capabilities and advanced high-speed interfaces has increased in PCBs, as well as for emulating ASICs using FPGAs on a PCB. The Cadence OrCAD and Allegro FPGA System Planner targets systems companies and IC companies who face challenges in using FPGAs on PCB Systems.
"Off-the-shelf multi-FPGA prototyping boards do not always meet the needs of designers," said Ed McGettigan, senior director of silicon hardware and applications at Xilinx, Inc. "Using this FPGA I/O synthesis technology, designers can create a new prototyping system while rapidly exploring multiple interconnect and component design alternatives much more quickly than by using typical manual methods for pin optimization."
The technology is available in a series of scalable solutions from the OrCAD FPGA System Planner to the Allegro FPGA System Planner L, XL and GXL tiers, and is tightly integrated with OrCAD Capture, OrCAD PCB Designer, Allegro Design Entry HDL and Allegro PCB Design products. The FPGA System Planner shortens the time it takes to integrate FPGAs on a PCB, enhances FPGA performance through the optimal utilization of FPGA resources, and can reduce PCB manufacturing costs through the reduction in the number of PCB layers required to route dense, complex, large pin-count FPGAs.
"The Cadence FPGA System Planner is an innovative solution for design teams facing the challenges of integrating today's large pin-count, complex FPGAs into the PCB design flow," said Charlie Giorgetti, corporate vice president at Cadence. "This is exactly the type of technology, automation and innovation our customers expect from us to reduce design cycles and manage risks with large pin-count FPGAs on PCBs."
OrCAD and Allegro FPGA System Planner products work with the 16.2 release and are available for customers to adopt immediately. For more information, visit http://www.cadence.com/cadence/newsroom/features/pages/feature.aspx?xml=fpga
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For more information, please contact: Dean Solov Cadence Design Systems, Inc. 408-944-7226 Email Contact