"The high-speed timing constraints of the PCS layer of the new USB 3.0 PHY require the highly capable design methodology offered by Encounter," said John Wilby, director of engineering-PHY, for the Snowbush IP Group at Gennum. "The move from a competitor's design environment to the Cadence Encounter Digital Implementation System took just three months from installation to first-pass silicon success. Key benefits with Encounter include its native signoff quality timing closure and support for advanced DFM rules in deep submicron technologies. In combination with low-power signoff, we also gained improved productivity, a high quality of silicon and ultimately faster time to market."
Wilby also noted that the fully integrated Encounter Digital Implementation System allowed Gennum to raise the bar on its design specifications and improve the competitive differentiation of its customizable family of IP cores through improved power savings and chip performance, reduced jitter, and optimized noise immunity.
The Encounter Digital Implementation System is a configurable and extensible high-performance, high-capacity, scalable design solution uniquely delivering flat and hierarchical design closure and signoff analysis, as well as low-power, advanced-node, and mixed-signal design solutions in a single integrated environment. The system also delivers interoperability with package, logic, and custom IC design. Cadence design-for-manufacturing (DFM) technologies are an integral part of the Encounter Digital Implementation System, enabling early identification, analysis and repair of yield-limiting design elements present at advanced nodes.
"Gennum's Snowbush IP Group has a strong track record of success, and we're pleased to play an integral role in the development of its latest high-speed family of customizable IP cores," said Chi-Ping Hsu, senior vice president of implementation research and development at Cadence. "This project was a success on multiple levels, but most notably it demonstrated that a full front-to-back design solution can be installed, ramped and used to deliver state-of-the-art advanced-node, low-power designs in a fraction of the time of previous solutions, with first-pass silicon success, lower risk, and faster time to market as the reward."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence and Encounter are registered trademarks and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact: Dan Holden Cadence Design Systems, Inc. 408-944-7457 Email Contact