Averant’s Solidify Sets New Standard in Verification of Digital Designs With Sequential Equivalency Checking and Automatic Testbench Synthesis
HAYWARD, Calif. — (BUSINESS WIRE) — April 20, 2009
Averant Inc., a leading provider of advanced verification technologies
for digital designs, today announces the release of Solidify 5.1, which
delivers new sequential equivalency checking (SEC) and automatic
testbench synthesis. Averant is the First In Formal™ leader in property
verification of RTL designs for digital integrated circuits.
Major improvements in Solidify 5.1 include:
SEC. Once a design’s functional goals are achieved,
engineers use sequential optimization techniques to improve power and
performance. These optimizations often rely on making complex
assumptions about the operating environment for portions of the
design. These assumptions and changes cannot be verified using current
equivalency checking tools. While property verification has been used
in the past for verifying these assumptions, Solidify 5.1 offers a
much improved solution to this challenging problem with enhanced
performance and ease of use.
Automatic Testbench Synthesis. Averant continues its advanced
verification leadership in Solidify 5.1 with an industry-first of
automatic testbench synthesis for easier functional simulation. Given
a design and an optional set of coverage targets, Solidify 5.1 can
generate a series of testbenches reaching all branches in the design
and the coverage targets. These testbenches assist functional
simulation by showing how hard-to-reach branches and coverage targets
can be exercised, and allow designers to run their RTL code in a
simulator without the burden of writing the testbenches themselves.
Improved Auto Checks. Averant’s industry leading auto checks
are used daily by design teams to catch bugs in design descriptions,
including dead code, deadlock, array boundary violation, signal
contention, clock domain crossing, and reset propagation. Solidify 5.1
contains significantly improved performance and robustness. Further
auto check enhancements will be delivered in future Solidify releases.
Improved Debugging. The debugging sub-system has been rewritten
to deliver a 10X improvement in performance in some cases for easier
analysis of large and complex designs.
“Optimizing a design for reduced power is now a basic necessity,”
commented Ramin Hojati, president of Averant. “Verifying the design has
the same behavior after optimization requires the use of a property
verification engine inside a sequential equivalence checker .
Additionally, property verification is needed to prove environmental
assumptions. With an integrated environment and the industry’s leading
and production-proven engines, the SEC capabilities in Solidify 5.1
enable users to develop golden RTL, and keep it functionally correct as
RTL edits are made to improve power and performance.”
Release 5.1 is available immediately, and includes sequential
equivalency features in pre-release form.
Averant Inc., founded in 1997, is a privately held EDA firm pioneering
new technologies for formal verification of digital designs. Averant’s
flagship product is Solidify, a robust platform for property, protocol,
and timing constraint verification, and for automatic design checks –
all without the need for simulators or test vectors. These tools are
easily adopted into the design flow, and help improve quality, reduce
risk, and speed the design process. For more information, see our web
Ramin Hojati, +1-510-581-8881 ext. 320