Sonics to Discuss Interconnect and SoC Challenges at Multicore Expo

MILPITAS, Calif.—(BUSINESS WIRE)—March 16, 2009— Sonics, Inc., a premier supplier of system-on-chip SMART Interconnect™ solutions, announces its participation in Multicore Expo, March 16-19 at the Santa Clara (Calif.) Convention Center.

Design architects will present two papers and take part in a panel about interconnect challenges during the three-day event.

Alex Chao, director of application engineering, will speak March 18 at 3:00 p.m. on “Using Multichannel DRAM Subsystems to Create Scalable Architectures for Video SoCs.”

Steve Hamilton, application architect, will be on a panel March 18 at 4:20 p.m. entitled, “Clock and Power Domain Control/Management Challenges in a Multicore World: The Interconnect Dilemma.”

Then March 19 at 1:00 p.m., Pascal Chavet, application architect, presents a paper entitled, “Requirements for SoC Analysis from Simulation to Silicon.”

Sonics will also be exhibiting in booth 8 on the show floor.

About Sonics

Sonics, Inc. provides SoC designers with critical semiconductor IP that is uniquely designed to optimize memory access and increase SoC performance in advanced digital consumer, wireless and mobile devices. Sonics' customers see the benefits of high design predictability and increased design efficiency. The company's broad array of on-chip connectivity solutions address the growing complexity found in consumer devices with advanced voice, data and video features. Major semiconductor and systems companies, including Broadcom, Samsung, Texas Instruments and Toshiba, leverage Sonics' technology in leading products in the wireless, digital multimedia and communications markets. For more information please visit

®Sonics, Inc., the company’s logo, and SMART Interconnect are registered trademarks of Sonics, Inc. All other trademarks are the property of their respective owners.


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