Averant Announces the New Generation of Static Functional Verification

Introducing a library of customizable automatic static checks, advanced source code debugging, and hierarchical functional verification

Solidify™ 2.5 includes
- Customizable automatic static checks
- Advanced source code debugging
- Enhanced hierarchical verification
- Automated constraint generation
- Property reuse and sharing
- Properties and labels embedded in HDL code

SUNNYVALE, CA, October 2, 2001 - Averant, Inc., the leader in static functional verification software for RTL level Verilog and VHDL designs, today announced the release of Solidify 2.5 for general distribution.

Solidify 2.5 introduces a library of standard design checks that automatically generate thousands of Solidify properties to find the most common static errors in designs. These checks include stuck-at-faults, deadlocked states and values, floating bus and bus contention, set-reset problems, full-case parallel-case violations, dead-code detection, and many more. These checks are written in Tcl and exploit Solidify's new open interface to its database. Now design and verification engineers can customize these checks and program in Tcl their own automatic checks for netlist and connection problems, design rule violations, and design specific hazards. All checks are performed using production proven technology taking full advantage of Solidify exhaustive static verification engine. Solidify 2.5 has advanced interactive source code debugging that links the conditions that cause a property to fail to specific HDL statements. When verifying a design, Solidify produces a table of values for the significant variables and clock cycles spanned by the failing property. When a value in the debug trace is selected, Solidify finds the line of HDL code that assigns that value to the variable and displays it.

Solidify's property checking approach to verification enables incremental verification as the HDL is written. Bugs can be found and fixed within moments of their creation. Design and verification can be done in parallel, reducing time-to-market and schedule risk while improving design quality. Solidify release 2.5 introduces features that makes this approach even more powerful and productive, thus enhancing support for hierarchical static verification. While developing and verifying a lower-level module in the hierarchy, its primary inputs will usually be constrained by higher-level modules. These input constraints can be specified and automatically applied to all of the properties used to verify the lower-level module. Latter when this module is instantiated in a higher-level module, Solidify 2.5 can automatically verify that the higher-level module does in fact constrain the signals as required. Additionally, properties developed at the block level can be verified as the block is used in higher-level blocks, making hierarchical verification and regression tests more automated.

Many formal and static functional verification tools often require tedious manual initialization of state variables to prevent properties from producing false negatives. In Solidify 2.5, specifying a reset sequence enables Solidify to automatically generate appropriate constraints, thus avoiding false negatives caused by impossible conditions. A user manual mode is also provided to help generate constraints for more complex behaviors. These new features also make Solidify more effective for black-box static functional verification.

Solidify 2.5 includes many other enhancements that make it easier to use while significantly improving verification productivity:

  • Enhancements to Averant's hardware property language (HPL) facilitate the parameterization, packaging, reusing, and sharing of properties.

  • Now HPL properties may be directly inserted in the HDL code. This enables Solidify to use HDL code structure to infer constraints for the HPL property. Properties can be inserted anywhere within sequential or combinatorial processes. Facilitates for reusing control structures in multiple code blocks in the same property is also provided.

  • Performance improvements have been made to the debug and verification engine with most test cases running significantly faster, thus shortening the debug cycle.

Solidify 2.5 is available on CD-ROM or FTP beginning October 2, 2001 and may be requested by email at info@averant.com. Solidify 2.5 will be sent to all Solidify customers that subscribe to maintenance. Solidify is available for PC's running Windows 95/98/NT4.0/2000 or Linux Red Hat 6.2 or later, and for workstations running Sun Solaris 2.6/2.7/2.8.

About Averant
Averant, Inc., founded in 1997, is a privately held EDA company pioneering the new methodology and technologies for static functional verification. Averant provides Solidify™, a design tool that delivers unprecedented performance in block-level verification for RTL designs. It is a high-capacity, static RTL analysis tool that verifies the functional behavior of Verilog or VHDL blocks without using simulators or test vectors.

Solidify improves design quality, reduces risk and uncertainty, shortens design cycles, and reduces the need for simulation based verification. Averant's products are easily incorporated into synthesis, IP reuse, and FPGA design flows.

Averant is on the web at www.averant.com, or can reached by email at info@averant.com.

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