SynTest Hybrid Solution Enhances Design Quality and Pattern Compactness

                                 “SynTest Patents for Staggered Capture technology Used for Optimization”

SAN JOSE, Calif., June 3, 2010 -- SynTest Technologies, Inc., a leading supplier of Design-for-Test (DFT) tools, announced optimization of the test patterns generated by its DFT tools by integrating the full power of SynTest Patents for Staggered Capture technologies.

Since 2005, SynTest has received many patents in DFT, some very fundamental, for Staggered Capture technologies used in Scan-ATPG and Logic BIST testing techniques. Now more of these patents are employed to achieve further optimization of test for detection of stuck-at, bridging, Iddq faults as well as delay faults.

Test optimization objectives are 3-fold – maximize fault coverage, minimize patterns and increase productivity of DFT engineers by minimizing pattern generation or application time for ATPG or LBIST. A hybrid scheme that employs patented “Staggered Capture” technology in the first phase and then switches to one-hot-capture is used to achieve the optimization. Low speed testing, for detecting stuck-at/bridging/Iddq faults, employs staggered single-capture followed by one-hot single-capture. Delay testing, for detecting transition and path-delay faults, employs staggered skewed-load (also known as launch-on-shift [LOS]) followed by one-hot skewed-load.

Dr. L.-T. Wang, founder, president, CEO of SynTest states, “Improving product quality with highest fault coverage and reducing test cost with more compact ATPG patterns are important to our customers. We are pleased to offer the hybrid DFT technology that helps our customers achieve their objectives.”

Staggered skewed-load, which applies on grouped clocks sequentially, generates near minimal number of patterns with fault coverage close to one-hot clocking. It detects intra-clock-domain as well as inter-clock-domain faults and achieves true at-speed testing even when there are asynchronous clocks. Further, pattern compression schemes with on-chip circuitry CAN be used for test cost reduction. Skewed-load requires multiple at-speed scan-enable signals, but today’s physical design systems can readily handle such constraints now. One-hot clocking applies only one grouped clock during each capture operation, but produces the highest fault coverage for intra-clock-domain faults.

Competing simultaneous skewed-load-capture schemes mask off unknown values at the originating scan cells or receiving scan cells across clock domains. Consequently pattern compression schemes may not be useable and it does not detect inter-clock-domain faults resulting in high fault coverage loss. It does generate the least number of patterns to detect inter-clock-domain faults. True at-speed testing is still achievable but it also requires multiple at-speed scan-enable signals.

“SynTest has consistently delivered improved versions of ATPG and Logic BIST tools that achieve all test optimization objectives,” added Dr. Ravi Apte, VP of Strategy, Marketing and Business Development of SynTest.

Patented staggered double-capture (also known as launch-on-capture LOC) technology has been used in SynTest TurboScan, VirtualScan, and TurboBIST-Logic for decades and is becoming ever more effective. This offers customers with easier to route Scan-enable signal that can be used in either ATPG or LBIST allowing easy switch between these two test methods on the same chip.

About SynTest
SynTest Technologies, Inc., established in 1990, develops IP for advanced design-for-test (DFT) and design-for-debug/diagnosis (DFD) applications and markets them throughout the world, to semiconductor companies, system houses and design service providers. The company has filed more than 38 US/PCT patents of which 17 have been issued and 1 allowed. The Company’s products improve an electronic design’s quality and reduce overall design and test costs. Various applications that use these IP (intellectual properties) include logic BIST, memory BIST, boundary-scan synthesis, Scan/ATPG with test compression, concurrent fault simulation, silicon debug and diagnosis. The company headquartered in Sunnyvale, California, has offices in Taiwan, Japan, Korea and China, and distributors in Europe and Asia including Israel. More information is available at

SynTest Technologies Inc. is headquartered at 505 South Pastoria Ave., Suite 101, Sunnyvale, California 94086, Phone: 408-720-9956, E-Mail: Email Contact

ATPG:       Automatic Test Pattern Generation
ATE:         Automatic Test Equipment
BIST:        Built-In Self-Test
DFT:         Design-for-Test
DFD:         Design-for-Debug/Diagnosis
IP:            Intellectual Property
TTM:         Time-to-Market


Ravi Apte,
Vice President, Marketing
408-720-9956 x 300

Review Article Be the first to review this article
Autodesk - DelCAM

Jeff RoweJeff's MCAD Blogging
by Jeff Rowe
Hexagon’s Recent Ups & Downs Update
Solidworks Product Designer for NASCENT Technology at Charlotte, NC
SYSTEMS INTEGRATOR for Palm Beach County Human Resources at West Palm Beach, FL
Developer-Support-Implementation Engineer for EDA Careers at San Francisco Area, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
AI·GI·CRV Conference 2017 at Edmonton, Alberta Canada - May 16 - 19, 2017
Innorobo 2017 at Docks de Paris Paris France - May 16 - 18, 2017
Display Week 2017 at Los Angeles Convention Center 1201 S Figueroa St Los Angeles CA - May 21 - 26, 2017
LiveWorx Tech Conf 2017 at Boston MA - May 22 - 25, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy Advertise