Cites Verific's Competency in Language Software Development
AT DAC Booth #655
Crossfire checks various views and formats of standard-cell libraries in an IC design-flow and validates that they all are alike. While Crossfire supported Verilog, it didn't support VHDL. Once Fenix-DA evaluated Verific's VHDL analyzer and implemented it with Crossfire, it replaced its internally developed Verilog analyzer with Verific's as well.
"Our core competency is in the analysis of layout and SPICE views, not the parsing of Verilog and VHDL models," says Chris Strolenberg, chief technology officer at Fenix-DA. "Rather than developing the expertise on our own, we chose to license the parsers from Verific. It was an excellent decision." Verific's products serve as the front end to the most popular EDA tools for exploring, navigating, analyzing, documenting and modifying designs, including Verilog, SystemVerilog and VHDL parsers, analyzers and elaborators, and an RTL database. All are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and come with support and maintenance. Verific will demonstrate its products at the 45th Design Automation Conference (DAC) in booth #655 June 9-12 at the Anaheim Convention Center in Anaheim, Calif.
"Fenix-DA is building a new class of EDA tools to give project teams more control over the time to market for their designs," remarks Rob Dekker, founder and president of Verific. "We're delighted to be part of this effort."
About Fenix Design Automation
Fenix-DA specializes in the validation of IP elements, starting with libraries and moving toward more complex IP structures. This technology is essential to maintain and improve the quality and consistency of the design flow. Fenix-DA has offices in The Netherlands and Sunnyvale, Calif. For more information, visit: www.fenix-da.com.
About Verific Design Automation
Verific Design Automation, with offices in Kolkata, India, and Alameda, Calif., is a leading provider of Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific's software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 30,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: http://www.verific.com.
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Public Relations for Verific