SynaptiCAD upgrades VeriLogger Extreme a fast compiled Verilog simulator

SynaptiCAD has released version 12.0 of it's compiled-code Verilog simulator and graphical HDL debugger, VeriLogger Extreme. New language features include support for switch primitives (nmos, pmos, tran, tranif0, etc) with strengths, Verilog-2001 generate statements, and $plusargs functions.

Better Breakpoints and Error Reports

New debugging features include signal and expression breakpoints, improved syntax checking and error reporting, and more features for navigating the source code using design information. The debugger has also been updated for the latest changes in 3rd party simulators, enabling users to quickly switch back and forth between different simulators to compare simulation results and uncover possible races in their design.

Graphical Test Bench Generation

One of VeriLogger Extreme's unique abilities is to generate Verilog test benches from waveform data acquired from logic analyzers, VCD files, or user-drawn waveforms. New test bench generation features include faster Verilog code generation and support of analog test bench signals for Actel's mixed-signal Fusion FPGAs.

Faster Compiles and Simulations

Several performance enhancements were also made to the simulator core and GUI: faster compile and simulation times (over 3x in many cases), reductions in memory footprint, faster VCD loading, and faster VCD waveform dumping.

Pricing and Availability

VeriLogger Extreme is available on Linux, Solaris, and MS Windows. A perpetual license sells for $4000 on Windows, but SynaptiCAD is offering an introductory discount of 25% for the next 90 days. Leasing options are also available, as well as a free, design-size limited version for student and classroom usage.

Marketing Contact

For any questions concerning this press release please contact Donna Mitchell at 540-953-3390 or email at donna@syncad.com. High resolution images can be downloaded directly from SynaptiCAD's web site at www.syncad.com.


Rating:


Review Article Be the first to review this article
HP

ACE2017

Featured Video
Editorial
Jeff RoweJeff's MCAD Blogging
by Jeff Rowe
Major Autodesk Disruption: Carl Bass Resigns
Jobs
Inside Sales for SolidCAM at Newtown, PA
Director of Mechanical Engineering for Velodyne LIDAR at Morgan Hill, CA
Architectural Designer II for AECOM at New York, CA
Architect for North County Transit District at Oceanside, CA
Architetural Project Manager for DRA Architects at Irvine, CA
Project Architect for LAMBERT Architecture and Interiors at Winston-Salem, NC
Upcoming Events
SOLIDWORKS 2017 Launch Event – Dudley at The Conference Hub, Dudley College of Technology, DY1 4AS Dudley United Kingdom - Feb 22, 2017
JEC World 2017 at Paris Nord Villepinte Exhibition Centre Paris France - Mar 14 - 16, 2017
SOLIDWORKS funding event – Leicester at The National Space Centre, Exploration Dr, Leicester, LE4 5NS Leicester United Kingdom - Mar 17, 2017
ACE 2017 Nashville at Nashville TN - Mar 21 - 23, 2017
SolidCAM: Patented Wizard to optimal feeds & speeds



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy Advertise