SynaptiCAD has released version 12.0 of it's compiled-code Verilog simulator and graphical HDL debugger, VeriLogger Extreme. New language features include support for switch primitives (nmos, pmos, tran, tranif0, etc) with strengths, Verilog-2001 generate statements, and $plusargs functions.
Better Breakpoints and Error Reports
New debugging features include signal and expression breakpoints, improved syntax checking and error reporting, and more features for navigating the source code using design information. The debugger has also been updated for the latest changes in 3rd party simulators, enabling users to quickly switch back and forth between different simulators to compare simulation results and uncover possible races in their design.
Graphical Test Bench Generation
One of VeriLogger Extreme's unique abilities is to generate Verilog test benches from waveform data acquired from logic analyzers, VCD files, or user-drawn waveforms. New test bench generation features include faster Verilog code generation and support of analog test bench signals for Actel's mixed-signal Fusion FPGAs.
Faster Compiles and Simulations
Several performance enhancements were also made to the simulator core and GUI: faster compile and simulation times (over 3x in many cases), reductions in memory footprint, faster VCD loading, and faster VCD waveform dumping.
Pricing and Availability
VeriLogger Extreme is available on Linux, Solaris, and MS Windows. A perpetual license sells for $4000 on Windows, but SynaptiCAD is offering an introductory discount of 25% for the next 90 days. Leasing options are also available, as well as a free, design-size limited version for student and classroom usage.
For any questions concerning this press release please contact Donna Mitchell at 540-953-3390 or email at firstname.lastname@example.org. High resolution images can be downloaded directly from SynaptiCAD's web site at www.syncad.com.