ALINT automatically extracts the synthesizable subset of verilog code and performs checks against the use of improper constructs for synthesis, incompletely specified conditional statements, potential problems with resource sharing in the synthesized netlist, simulation/synthesis mismatches, such as incomplete sensitivity lists or functions, mistakes with multiple assignments to the same signal.
A built-in synthesis emulation framework automatically converts extracted RTL to the verilog netlist model and allows detection of unwanted latches and flip-flops with fixed values on the inputs, detection of problems with asynchronous controls of inferred flip-flops and issues with inferences of tri-state buffers.
ALINT is also capable of performing the checks at the chip netlist level by analyzing the netlist model of the whole chip. Analyzing the whole chip allows for the monitoring of typical DFT problems, such as the influence of global clock signals on non-clocking ports, uncontrollability of clocks, unwanted synchronous feedbacks and unwanted direct connections of flip-flop/latch outputs to control lines of other storage elements.
The new ALINT option is fully integrated with Aldec's Riviera 2007.06 simulator. ALINT is available today on Windows, Linux-32/64 and Sun platforms.
Semiconductor Technology Academic Research Center (STARC) was established in December 1995 with investment from Japan's leading semiconductor suppliers to reinforce semiconductor design capability.
Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux, Solaris and Windows platforms. www.aldec.com
ALINT is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Aldec, Inc., Henderson
Dave Rinehart, 702-990-4400