Also, Calypto will offer demonstrations of its low-power solutions, including new PowerPro(TM) CG (Clock Gating) and SLEC(TM) (Sequential Logic Equivalence Checking), during the Microprocessor Forum Expo and Demo Showcase Tuesday, May 22, from 5-8 p.m.
PowerPro CG reduces power consumption by applying sequential analysis at the register transfer level (RTL) to identify micro-architectural optimizations for a lower power circuit. By analyzing the sequential behavior of synthesizable RTL across multiple clock cycles, it identifies regions of a chip that can be clock gated to reduce dynamic power. PowerPro then automatically generates the clock-gating enable logic, providing consistently better results in significantly less time than the error prone, time consuming manual techniques used by design teams today.
For more details on Calypto, SLEC and PowerPro CG, visit: http://www.calypto.com.
Information on the In-Stat Microprocessor Forum can be found at: http://www.instat.com/mpf/07/.
Founded in 2002, Calypto Design Systems, Inc. enables SoC design teams to bridge System and RTL for semiconductor design, saving millions of dollars in design costs and silicon re-spins. It delivers software products to leading edge semiconductor and systems companies worldwide. Calypto is privately held with venture funding from Cipio Partners, JAFCO Ventures, Tallwood Venture Capital and Walden International. It is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program and the Mentor Graphics OpenDoor program. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. Email: email@example.com. More information about Calypto may be found at: www.calypto.com
Calypto, PowerPro and SLEC are trademarks of Calypto Design Systems Inc. Other products and company names may be trademarks or registered trademarks of their respective companies.
Nanette Collins, 617-437-1822
Public Relations for Calypto Design Systems