The speedup and capacity improvements increase based on the size and complexity of the design. In a recent tapeout support, the dynamic simulation run-time was reduced from 14 hours 30mins to 6 hours 38mins on a 65nm design with 8M gates. On a larger design with 110M gates, RedHawk-EV version 5.3 delivered an even more significant runtime speedup with a total run-time reduction from 58 hours to that of 12 hours running on a 64-bit machine. This was a highly complex design whose analysis included a RDL (Re-Distribution Layer) with complex power routings and with on-chip memories fully modeled down to the lowest level of metal.
"As design size and complexity increases, the tools used by customers to validate their designs need to keep pace with their demands," said Dian Yang, vice president of product management at Apache. "In spite of our significant competitive lead in runtime and capacity, Apache continues to enhance our products and technologies to meet the needs of our customers' most challenging designs."
"The latest enhancements in performance and memory are obtained from upgrades of our core physical database, extraction engine, and simulation kernel with no impact on waveform accuracy," said Andrew Yang, CEO of Apache Design Solutions. "The new version improves customers' productivity by significantly reducing the overall turnaround time of deploying full-chip dynamic solutions to SoC designs at 65nm and below."
Apache will be demonstrating RedHawk-EV, along with their complete power integrity and noise management solutions, at the upcoming Design Automation Conference (DAC) in San Francisco, California, July 24 - 27, in booth #1906.
RedHawk-EV version 5.3 is immediately available for customer use. All existing RedHawk-EV customers will automatically receive version 5.3 as part of their maintenance.
RedHawk is a full-chip Vectorless Dynamic(TM) physical power integrity solution for SoC power closure sign-off of 130nm, 90nm, and 65nm designs. Certified by TSMC's 5.0 and 6.0 Reference Flow and correlated with silicon measurements and SPICE, RedHawk addresses dynamic power issues such as simultaneous switching output (SSO) for core, memory, clock, and I/O, as well as effects of on-chip inductance, package RLC, and decoupling capacitance. RedHawk delivers transistor-level accuracy with cell-based capacity, performance, and ease-of-use.
With RedHawk designers can identify dynamic "hot spots," examine the impact on timing, accurately pinpoint the cause of dynamic voltage drop, and automatically repair the source of supply noise. RedHawk enables designers to reach power closure sign-off for high performance SoCs, including those utilizing advanced low-power design techniques such as leakage current control, MTCMOS (power-gating), multiple voltage domains, and multiple threshold transistors.
About Apache Design Solutions
Apache is an EDA software supplier of innovative next-generation silicon integrity platforms for low-power, high-performance system-on-a-chip (SoC) designs. By considering all sources of noise that impacts the design--such as power, signal, package / system IO, substrate, and temperature--Apache's silicon signoff platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon. Apache's vendor-neutral platform enables designers to adopt any industry-standard physical design flow and is certified by TSMC's 5.0 and 6.0 Reference Flow (NYSE:TSM).
Apache has direct sales and support offices worldwide with over 40 customers, including 7 of the top 10 semiconductor companies. For more information, visit www.apache-da.com.
Apache Design Solutions, NSPICE, RedHawk, PsiWinder, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.
Apache Design Solutions Yukari Chin, 650-641-4200 Email Contact or Public Relations for Apache Cayenne Communication Michelle Clancy, 252-940-0981 Email Contact