Celestry Introduces Cell Noise Characterization Software, Socle Selects Celestry for Sign-off

Nautilus-SI and CellXpert-CN Pair Up for Accurate Signal Integrity Sign-Off



SAN JOSE, California-April 8, 2002 - Celestry Design Technologies, Inc., the leading provider of Silicon Accurate Sign-off™ technology for the semiconductor and electronics industry, announced today that it is shipping the first member of its cell noise characterization family of products-CellXpert-CN™.

In addition, Celestry announced that Socle Technology Corp. (Hsin-Chu, Taiwan), a TSMC Design Center Alliance company, has selected CellXpert-CN for cell noise characterization and Celestry's Nautilus-SI™ for signal integrity sign-off by Socle's RTL2Silicon service.

CellXpert-CN eliminates cell noise library characterization iterations by using an algorithm that reduces the effort to a single pass. It also reduces the amount of false errors during signal integrity analysis and speeds design debug to increase productivity.

"After a detailed evaluation of Nautilus-SI and CellXpert-CN's cell library noise characterization, we found the methodology fits well with our SoC-ImP™ technology, and gives us the best solution for our cell-based signal integrity analysis sign-off," remarked, Mr. David Lyou, Socle's General Manager.

"After a detailed evaluation of Nautilus-SI and CellXpert-CN's cell library noise characterization, we found the methodology fits well with our SoC-ImP™ technology, and gives us the best solution for our cell-based signal integrity analysis sign-off," remarked, Mr. David Lyou, Socle's General Manager.

Zhihong Liu, President and CEO of Celestry noted, "As part of our Silicon-Accurate Sign-off efforts, CellXpert-CN is the first product in our noise characterization family. Later this year, we will introduce more noise characterization products for intellectual property, memory and analog mixed-signal designs."

About Nautilus-SI
For SoC design, Nautilus-SI offers full-chip signal integrity verification software for deep submicron multi-million cell designs. It incorporates 3D parasitic extraction technology to accurately determine coupling capacitance. With its delay analysis engine, it captures coupling effects on timing and identifies signal integrity problems due to coupling noise.

Price and Availability
Celestry's CellXpert-CN with Nautilus-SI is available now. Nautilus-SI with CellXpert-CN starts at $115K for a time-based license (TBL). The software runs on Sun Solaris.

About Socle Technology Corp.
Since its inception in June 2001, Socle has focused on developing its own platform based technologies (SoC-ImP™ and mPlatform™) and deploying the design services derived with the vision to become the worldwide leader of the SoC design platform solutions provider. Socle works with foundries, EDA, library/IP providers and other service partners to provide the best-fit solutions and services to customers. Its SoC-ImP™ environment provides the most advanced and optimized deep submicron (DSM) SoC design flow methodology for RTL2Silicon service based on world leading EDA tools. Socle is a member of TSMC's Design Center Alliance. For more information, please visit www.socle-tech.com.tw

About Celestry
Celestry is the leading provider of physical design and analysis products that enable integrated circuit designers to achieve optimal performance from semi conductor process technologies. The Company offers software and services to electronic and semiconductor companies involved with the design of chips that are used in networking, communication, multimedia and computing products. For more information, visit www.celestry.com or email Email Contact.


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Notes to Editors

Acronyms and definitions:

.lib Synopsys library format
CN: Cell Noise
IC: Integrated Circuit
I/O: Input/Output
nlib: Celestry noise library format
RC: Resistance and Capacitance, refers to parasitic R's and C's in IC interconnect
SI: Signal Integrity
RTL or RT-level: Register Transfer Level
SPICE: Industry standard circuit simulator
SPICE/CDL: Cadence SPICE netlist format
tlf: Cadence library format , a table-based timing model format for gate-level
calculation of gate load delay and gate output slew


Celestry, the Celestry logo, CellXpert-CN, Nautilus-SI and Silicon-Accurate Sign-off are trademarks of Celestry Design Technologies, Inc. All other trademarks and tradenames are the property of their respective owners.



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