Altera's Dr. Misha Burich to Present SDR Forum Keynote Address on FPGAs and System-Level Optimization

    SAN JOSE, Calif., Nov. 9 /PRNewswire-FirstCall/ --

     What:     Dr. Misha Burich, Altera Corporation's (NASDAQ: 
ALTR) senior
               vice president of software and systems engineering, will
               deliver the keynote address at SDR Forum this year. He will
               discuss FPGA design methodologies for system-level optimization
               within military and wireless applications.

               These FPGA-based methodologies enable designers to focus on
               refining design at the system level while streamlining design
               implementation. They extend the modern back-end register
               transfer level (RTL) design flow used for FPGAs by integrating
               higher-level languages and tools, embedded processors and
               intellectual property (IP) cores. Technical experts from Altera
               will also deliver presentations on power management, hardware
               acceleration and design security.

               In addition, Altera will be showcasing the following
               demonstrations in booth 211 on the exhibition floor:
                 --  A reconfigurable multi-standard equalizer created using
                     high-level FPGA design methodologies
                 --  A WiMAX platform utilizing the hardware co-simulation
                     feature of Altera's DSP Builder design software to verify
                     operation of the RTL reference design from a system-level

     When:     Keynote address, Tuesday, November 15, 2005 at 8:30 a.m.

     Tuesday, November 15, 2005

     8:30 - 9:20 a.m.      Keynote Address: FPGA and Structured ASIC Design
     Royal Ballroom        Methodologies for SDR Applications
                           Dr. Misha Burich, Senior Vice President of
                           Software & Systems Engineering

     1:30 - 4:00 p.m.      Paper: Low-Power Software-Defined Radio Using FPGAs
     Plaza Terrace         Joel Seely, Technical Manager

     Thursday, November 17, 2005

     9:30 - 11:30 a.m.     Paper: Power Comparison of Architectural Choices
     Plaza Terrace         on Waveform Development
                           Joel Seely, Technical Manager

     9:30 - 11:30 a.m.     Paper: Design Security with Waveforms
     Royal Ballroom A      Jie Feng, Product Line Manager

     1:30 - 4:00 p.m.       Paper: The Use of Hardware Acceleration in SDR
     Plaza Terrace          Waveforms
                            David Lau, Software Engineer

     Where:          Hyatt Regency Orange County
                     11999 Harbor Blvd.
                     Booth 211
                     Garden Grove, CA 92840

                     For additional show information visit:

     Contact:        Bruce Fienberg
                     Altera Corporation
Email Contact

NOTE: Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holder.

CONTACT: Bruce Fienberg of Altera Corporation, +1-408-544-6397, or
Email Contact

Web site:


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