Avertec's solution for Timing and SI sign-off at DAC, Booth 256

At DAC'05, Avertec is presenting HiTAS 6.7, the latest version of its transistor-level Timing & Signal-Integrity platform.

Avertec offers solutions for the back-end verification of complex designs with its transistor level methodology based on proven HiTAS and YAGLE platforms.

HiTAS platform provides advanced Static Timing Analysis and Signal Integrity solutions at transistor level. It allows engineers to ensure complete timing and Signal Integrity coverage on digital custom designs and IP-reuse through timing characterization.

YAGLE's unique ability is to provide timing back-annotated HDL descriptions, close to physical implementation, enables the setup of solutions based on signal activity, such as power consumption or IR-drop analysis.

About Avertec
Avertec is a privately held company created in 1998 and headquartered in the Paris area, France. It has a sales office in San Jose, California and represented by distributors in Japan and in Asia. Avertec is a member of the EDA Consortium. Further information at http://www.avertec.com


Contact at DAC booth#256: Rita Kupi
Cell: +33 6 61 78 59 65




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