Avertec's modeling engine is based on a topological partitioning of the design. Partitions are modeled as current sources with semi-analytical equations, with transistor's current equations coming from BSIM models. Avertec's CSM then offers orders of magnitude gains in runtime versus electrical simulation, while keeping SPICE accuracy.
Within its timing and signal integrity technology, it allows fast delay calculation for arbitrary sets of process, voltage, temperature (PVT), as well as precise modeling of the effective load of long interconnects. Furthermore, Avertec's CSM is independent from the input waveform shape, and can advantageously replace rejection tables, allowing efficient noise propagation, and avoiding the extra pessimism inherent to traditional crosstalk analysis methodologies.
The HiTas platform has been adopted by major European semiconductor vendors to perform SI-aware timing characterization of custom macros, and fast re-characterization of cell libraries for any set of PVT.
Avertec's timing characterization is ready to support Synopsys Composite Current Source (CCS) and Cadence/Magma Effective Current Source Model (ECSM) formats.
Avertec is a privately held company created in 1998. The company provides transistor-level Static Timing Analysis (STA) and Signal Integrity (SI) tools, dedicated to digital custom designs. Avertec has an innovative Transistor level methodology based on proven HiTAS and YAGLE platforms.
The company is headquartered in the Paris area, France, has a sales office in San Jose, California and represented by distributors in Japan and in Asia. Avertec is a member of the EDA Consortium. Further information at http://www.avertec.com
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Tel: +33 1 60 92 16 32