Creonic to Supply New LDPC Decoder and Encoder IP Cores for CCSDS Standard

Kaiserslautern, Germany, Apr. 30 2015 – Creonic GmbH, a leading IP core provider for communications, announced today the release of their new CCSDS LDPC encoder and decoder IP cores for the satellite and backhaul markets. The IP core complements the company's broadest product portfolio of LDPC IP cores in the world.

ccsds ldpc decoderThe CCSDS LDPC codec supports code rate 223/255 with coded block size of 8160 bits, which allows for a simple replacement of legacy Reed-Solomon decoders. It was designed particularly for near-earth space missions, but the excellent error correction performance makes it the ideal fit for additional high-throughput applications such as microwave or optical links.

The new CCSDS LDPC IP cores are low-power and low-complexity designs. The decoder has a layered architecture that allows for twice as fast convergence behavior and half the latency when compared to state-of-the-art solutions. Decoder and encoder perform with 1.6 Gbit/s coded throughput when operating at 200 MHz. Decoding latency is 4.3 µs while the encoding latency is only 40 ns.

The LDPC decoding algorithm gains more than 2.5 dB against Reed-Solomon-based solutions of the same code rate. This gain allows for more reliable data transmission, less power consumption or for an increased transmission range.

The IP cores are available for ASIC and FPGA (Xilinx and Altera) technologies either as source code or encrypted source code. In addition, the cores come with HDL simulation models, VHDL or SystemC testbench, bit accurate Matlab, C or C++ simulation model and comprehensive documentation.

For more information, please visit the product page or contact us.

About Creonic

Creonic is an ISO 9001:2008 certified provider of ready-for-use IP cores for communications systems design and for complex signal processing functions such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. Creonic’s product portfolio covers standards that include DVB-S2X, DVB-RCS2, WiFi, WiGig, and UWB. These cores are applicable for ASIC and FPGA designs. For more information, please visit www.creonic.com.

Contact

Senay Unal

Manager, Marketing and Sales

Email Contact

+49 631 3435 9886



Read the complete story ...


Review Article Be the first to review this article
Featured Video
Editorial
Jeff RoweJeff's MCAD Blogging
by Jeff Rowe
GE Additive’s Big Plans For Metal AM
Jobs
ECAD Designer - Data Connectivity for Delphi at Auburn Hills, MI
Mechanical Engineer II - Requisition ID 090445 for L3 Technologies at New York, NY
Estimator / Bidder for Rulon International at Saint Augustine, FL
Upcoming Events
33rd Annual Coordinate Metrology Society Conference at Snowbird UT - Jul 17 - 21, 2017
EMO Hannover 2017 at Hannover Germany - Sep 18 - 23, 2017
The 30th Annual Integrated Process Excellence Symposium & Training at Wyndham Grand Bonnet Creek Resort Orlando FL - Sep 18 - 20, 2017
Additive Manufacturing Conference 2017 at Knoxville Convention Center 701 Henley Street Knoxville TN - Oct 10 - 12, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy Advertise