Kaiserslautern, Germany, Apr. 30 2015 – Creonic GmbH, a leading IP core provider for communications, announced today the release of their new CCSDS LDPC encoder and decoder IP cores for the satellite and backhaul markets. The IP core complements the company's broadest product portfolio of LDPC IP cores in the world.
The CCSDS LDPC codec supports code rate 223/255 with coded block size of 8160 bits, which allows for a simple replacement of legacy Reed-Solomon decoders. It was designed particularly for near-earth space missions, but the excellent error correction performance makes it the ideal fit for additional high-throughput applications such as microwave or optical links.
The new CCSDS LDPC IP cores are low-power and low-complexity designs. The decoder has a layered architecture that allows for twice as fast convergence behavior and half the latency when compared to state-of-the-art solutions. Decoder and encoder perform with 1.6 Gbit/s coded throughput when operating at 200 MHz. Decoding latency is 4.3 µs while the encoding latency is only 40 ns.
The LDPC decoding algorithm gains more than 2.5 dB against Reed-Solomon-based solutions of the same code rate. This gain allows for more reliable data transmission, less power consumption or for an increased transmission range.
The IP cores are available for ASIC and FPGA (Xilinx and Altera) technologies either as source code or encrypted source code. In addition, the cores come with HDL simulation models, VHDL or SystemC testbench, bit accurate Matlab, C or C++ simulation model and comprehensive documentation.
Creonic is an ISO 9001:2008 certified provider of ready-for-use IP cores for communications systems design and for complex signal processing functions such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. Creonic’s product portfolio covers standards that include DVB-S2X, DVB-RCS2, WiFi, WiGig, and UWB. These cores are applicable for ASIC and FPGA designs. For more information, please visit www.creonic.com.
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