PLDA and Avery Design Systems Cooperate on PCI Express

TEWKSBURY, Mass. — (BUSINESS WIRE) — March 2, 2015 — Avery Design Systems Inc., a leader in verification IP, today announced PLDA and Avery Design Systems have engaged in collaboration to facilitate interoperability of PCI-Xactor VIP and XpressRICH IP and perform extended compliance validation using Avery PCIe compliance test-suite.

“We have been pleased to collaborate with Avery Design to support the validation of our XpressRICH3 IP using the Avery Design testbench and compliance tests on behalf of our mutual customers,” said Stephane Hauradou, CTO, PLDA. “We are now pre-qualified with Avery VIP and have enhanced the quality of our IP in the process which is important for customers seeking the proven, interoperable solutions.”

Avery Design supports over 35 standard protocols ranging from high speed IO, SSD/HDD, mobile, embedded storage, memory, and control bus protocols. Avery Design VIPs offer the most complete verification solutions consisting of System Verilog UVM compliant models and environment, protocol checkers, directed and random compliance test suites, and reference verification frameworks. Advanced debug features include multi-level analyzer trackers to visualize data and control flow through the protocol stacks. Compliance verification services are offered for all VIPs.

“Avery Design is pleased to collaborate with PLDA, a leading PCIe IP provider. Pre-qualifying XpressRICH3 IP with Avery VIP Solutions enables customers to reduce time of their design and verification cycles,” said Chilai Huang, president of Avery Design Systems.

Visit Avery Design at DVCon on March 2-5, 2015 at the Doubletree Hotel, San Jose, CA in booth #904 to learn more about Avery Design VIP solutions.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation, low power retention register synthesis, and RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, HMC, ONFI/Toggle, NVM Express, SCSI Express, SATA Express, eMMC, SD/SDIO, and CAN FD standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.



Contact:

Avery Design Systems
Chris Browy, 978-689-7286
Email Contact




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