Cadence Achieves First PCI Express 2.0 and PCI Express 3.0 Compliance for TSMC 16nm FinFET Plus Process

Multi-protocol PHY supports PCI Express 2.0, PCI Express 3.0, USB 3.0 and SGMII specifications

SAN JOSE, Calif., Feb. 25, 2015 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its multi-protocol Serializer/Deserializer (SerDes) PHY IP for PCI Express® (PCIe®) 2.0 and PCIe 3.0 technology for TSMC's 16nm FinFET Plus (16FF+) process have passed PCI-SIG® compliance testing. The complete solution of PHY and controller achieved compliance just 12 months after the announcement of the 16FF+ process. Achieving PCI-SIG compliance further boosts designers' confidence that the Cadence IP will operate to the specification, when integrated in their system-on-chip (SoC) designs.

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For more information on Cadence IP for PCIe offerings, please visit: http://www.cadence.com/news/PCIeIP

"As a PCI-SIG member for more than 10 years, Cadence has played a role in promoting the adoption of PCIe technology," said Al Yanes, president and chairman of PCI-SIG. "By participating in the compliance program, Cadence is helping to ensure PCIe ecosystem interoperability."

The multi-protocol PHY enables designers to make performance and system cost tradeoffs while reducing risk and shortening design cycles. The support of multiple protocols enables creation of flexible SoCs that can be configured to different standards via software, extending the application of a single tapeout. Design schedules and cost are minimized by reducing the number of PHYs to evaluate, integrate, and characterize.

"PCIe 3.0 and PCIe 2.0 compliance was achieved with first 16FF+ silicon. The early availability of these products enables our customers to tapeout their leading-edge mobile, storage and enterprise designs sooner and with reduced risk," said Osman Javed, product marketing director at Cadence. "These flexible multi-protocol solutions provide customers a unique combination of SoC differentiation and future proofing."

"As part of its successful PCIe compliance testing, Cadence utilized the leading-edge PCIe 2.0 and PCIe 3.0 test and development tools from Teledyne LeCroy," said Joe Mendolia, vice president of marketing at Teledyne LeCroy. "This is the latest example of many years of the close relationship between the two companies on comprehensive compliance testing that enables designers to confidently integrate high-speed PCIe interfaces into their SoCs."

About Cadence

Cadence (NASDAQ: CDNS) enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries.  All other trademarks are the property of their respective owners.

PCI-SIG, PCI Express, and PCIe are trademarks or registered trademarks of PCI-SIG. 

For more information, please contact:
Cadence Newsroom
408-944-7039
Email Contact

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To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/cadence-achieves-first-pci-express-20-and-pci-express-30-compliance-for-tsmc-16nm-finfet-plus-process-300040830.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com




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