AUSTIN, Texas — (BUSINESS WIRE) — February 19, 2015 — The Silicon Integration Initiative’s (Si2) Compact Model Coalition (CMC) is pleased to announce the addition of two new SPICE model standards for Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs. These compact models are based on the popular University of California at Berkeley Short-channel IGFET Model (BSIM) and on the Hiroshima University STARC IGFET Model (HiSIM) compact model platforms.
FDSOI is a scalable CMOS roadmap technology for 28nm and below for integrated device manufacturers (IDMs) and foundries. Fully Depleted SOI technology has been referred to using multiple names in the literature and on the web. Alternative names include ETSOI (Extremely Thin Silicon-On-Insulator), UTB (Ultra-Thin Body), UTBB (Ultra-Thin Body and Buried oxide), SOTB (Silicon On Thin Buried oxide). Regardless of the name, the new models will cover the modeling needs of advanced thin body, thin buried oxide SOI transistor technology. Partially-depleted (PD) and dynamically-depleted (DD) SOI users will continue to have their standard compact model needs met by existing CMC standard models BSIM-SOI and HiSIM-SOI.
The two new FDSOI compact models, called BSIM Independent Multi-Gate (BSIM-IMG) and HiSIM Silicon-On-Thin-Buried-oxide (HiSIM-SOTB) models, have been rigorously tested by CMC member companies for functionality, data fitting accuracy and circuit simulation numerical robustness. Both models are now supported in commercially available circuit simulators that support Verilog-A. Model descriptions along with Verilog-A model codes and user manuals for all of the CMC standard models mentioned in this press release including the new FDSOI models are accessible to the public through this Si2 link: http://www.si2.org/?page=1684
University of California at Berkeley Professor Dr. Chenming Hu, inventor of the 3D transistor, leads a research team that has been deeply embedded in developing simulation models for the semiconductor industry. He states, “BSIM-IMG models the electrical characteristics of the independent double-gate structure. Ultra-thin body transistor was proposed and demonstrated by the same group at the same time as FinFET. Now this other sub-25nm technology is also supported by Si2 standard model for IC design.”
Hiroshima University Professor Dr. Mitiko Miura-Mattausch, developer of the first surface-potential-based model practically applicable for real circuit simulations, leads a research team that is involved in supplying simulation models for different semiconductor device types to the electronic industry. She states, “HiSIM-SOTB is the ultimate model, not only for SOTB transistors, but capable to cover a wide range of different structures including bulk- and DG-MOSFET.”
Being chosen as an industry standard by the CMC members is an extensive and rigorous process. Candidate models are first solicited from academia and initially vetted by a CMC work group. Approved candidate model(s) are evaluated based on how well the model can fit industry provided transistor-level data and on how well the model functions in vendor circuit simulators. A QA suite is created for each standard model to ensure that a vendor simulator compiled-code model implementation matches the model developer’s intentions. Model developers whose compact model is selected as a CMC standard will have their model supported by CMC funding for continued model development and maintenance. The CMC will provide financial support and CMC members will collaborate with Dr. Hu and Dr. Miura-Mattausch to enhance BSIM-IMG and HiSIM-SOTB respectively. Periodic updates to these CMC standards will be released in a coordinated manner following CMC protocols as model enhancements are developed and qualified.
Si2 is the largest organization of industry-leading semiconductor, systems, EDA and IDM companies focused on the development and adoption of standards to improve the way integrated circuits are designed and manufactured. Now in its 27th year, Si2 is uniquely positioned to enable timely collaboration through dedicated staff and a strong implementation focus driven by its member companies. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world. Please visit our website at: www.si2.org
Silicon Integration Initiative (Si2)
William Bayer, 512-342-2244 x304