Synopsys' New DesignWare DDR Explorer Tool Delivers Up to 20 Percent Improvement in DDR Memory Subsystem Efficiency

Performance Analysis Tool Accelerates Optimization of Address Mapping, Clock Frequency and Quality of Service for DesignWare DDR Memory Controller

MOUNTAIN VIEW, Calif., Feb. 11, 2015 — (PRNewswire) —

Highlights:

  • DesignWare DDR Explorer enables designers to optimize memory subsystems for power, performance and cost through a graphical simulation and analysis environment
  • Explore and adjust Synopsys' DesignWare DDR Memory Controller configurations to achieve up to 20 percent improvement in memory bandwidth
  • Optimize address mapping, clock frequency and quality of service to select lower cost, lower power DRAM memories
  • Achieve 10X faster turnaround time compared to RTL analysis with transaction-level simulation to visualize performance and conduct performance sensitivity analysis

Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced the new DesignWare® DDR Explorer performance analysis tool, which enables designers to quickly optimize Synopsys' DesignWare Enhanced Universal DDR Memory Controller (uMCTL2) for performance, power and cost. Using DDR Explorer, designers can analyze their DDR memory subsystem and optimize their architecture to increase efficiency by up to 20 percent, while achieving 10X faster turnaround time compared to RTL analysis. With the graphical simulation and analysis provided by DDR Explorer, designers can quickly select the right memory type for the lowest bill of material (BOM) cost and system power. DDR Explorer supports all of the industry standard DRAM interfaces for mobile and enterprise applications, including LPDDR2, LPDDR3, DDR2, DDR3 and DDR4.

DDR Explorer integrates a transaction-level architecture model of the DesignWare DDR Enhanced Universal Memory Controller with a graphical simulation and analysis environment that enables designers to define, run and analyze hundreds of scenarios to identify the best memory controller configuration. RTL-based performance checking, while required for final validation, typically has longer turnaround times and limits the practical number of design explorations during a project to fewer than 25. DDR Explorer enables thorough performance and power sensitivity analysis for over 250 simulations in the same amount of time. By identifying heavy traffic conditions and bottlenecks, designers can explore the DDR memory controller parameter configurations and register settings to optimize the DDR memory performance. This results in up to 20 percent greater memory efficiency, lower power consumption and lower memory cost, without sacrificing other memory performance requirements. The optimized configuration from DDR Explorer is used for DDR memory controller RTL IP configuration and performance validation, speeding the implementation and verification of the IP.

"With DDR Explorer, designers can rapidly configure, simulate and analyze the DDR memory controller and PHY subsystem," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "DDR Explorer enables designers to significantly reduce the effort of integrating DesignWare DDR Enhanced Universal Memory Controller and PHY IP into their SoCs for faster time-to-market."

Availability & Resources

DesignWare DDR Explorer is available now.

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, analog IP, complete interface IP solutions consisting of controller, PHY and next-generation verification IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and customized IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at http://www.synopsys.com.

Editorial Contacts:
Tess Cahayag
Synopsys, Inc.
650-584-5446
Email Contact

Stephen Brennan
MCA, Inc.
650-968-8900, ext.114
Email Contact

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/synopsys-new-designware-ddr-explorer-tool-delivers-up-to-20-percent-improvement-in-ddr-memory-subsystem-efficiency-300034169.html

SOURCE Synopsys, Inc.

Contact:
Synopsys, Inc.
Web: http://www.synopsys.com




Review Article Be the first to review this article
HP

Autodesk - DelCAM

Featured Video
Jobs
CAD Systems Administrator for KLA-Tencor at Milpitas, CA
Senior Mechanical Engineer for Verb Surgical at Mountain View, CA
Principal Research Mechatronics Engineer for Verb Surgical at Mountain View, CA
Lead Geospatial Analyst for Alion at McLean, VA
Industrial Designer Intern – Spring 2017 for Nvidia at Santa Clara, CA
Upcoming Events
SOLIDWORKS 2017 Launch Event – Walsall at Village Hotel Club, Walsall, WS2 8TJ Walsall United Kingdom - Mar 30, 2017
PI APPAREL Hong Kong 2017 at SHANGRI-LA KOWLOON 64 Mody Road Tsim Sha Tsui East Kowloon Hong Kong - Apr 5 - 6, 2017
SOLIDWORKS intro and hands on session – Slough at Baylis House, Slough, Berkshire, SL1 3PB Slough United Kingdom - Apr 7, 2017
Engineer 3D! Training + Technology Conference at Hyatt Regency Milwaukee 333 West Kilbourn Avenue Milwaukee WI - Apr 25 - 26, 2017
MasterCAM



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy Advertise