Aldec Announces HES-7, the Largest Off-The-Shelf Xilinx Virtex-7 FPGA Prototyping System at up to 288 Million ASIC Gates Capacity

HENDERSON, Nev. — (BUSINESS WIRE) — February 9, 2015Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, today unveils the largest in the industry, off-the-shelf Xilinx® Virtex®-7 prototyping system for SoC and ASIC designs, offering up to 288 million ASIC gates capacity. The newest board, HES-7™ (HES7VX12000BP), contains six Xilinx Virtex-7 2000T FPGAs in FLG1925 package delivering up to 72 million ASIC gates capacity per board, and by adding up to three additional boards, the FPGA prototyping system is scalable up to 288 million ASIC gates with the Aldec Backplane (HES7-BPx4).

“We are pleased with the expansion of the HES-7 family,” said Zibi Zalewski, General Manager of Aldec’s Hardware Products Division. “We began backplane-based prototyping architecture with dual Virtex-7 2000T boards that offered the ability to scale up to eight FPGAs. Today our newest board is the largest turnkey, off-the-shelf Virtex-7 prototyping board with six FPGAs on the single board and up to 24 with Backplane configuration, giving capacity, interconnections and scalability to accommodate the largest SoC projects.”

The new HES-7 FPGA board provides nine FMC connectors, a total of 648 differential pairs for external FMC compliant daughter cards (legacy or new hardware), while internal FPGA to FPGA connections are a total of 977 differential pairs per board with an additional common bus for debugging purposes. The control FPGA Xilinx Virtex-7 690T is now connected with high speed interfaces such as Ethernet 1 GB and 40 GB (QSFP+), USB3.0 and PCIe x16/x8 for the most advanced design support.

HES-7 can be used for traditional high speed prototyping with a control utility for FPGA programming and board configuration. HES-7 also offers the unique advantage of serving as a hardware platform for advanced verification modes of Aldec HES-DVM™ simulation acceleration and emulation without requirements for dedicated hardware.

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About Aldec

Aldec, Inc., established in 1984 and headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware Emulation, Hardware Acceleration, FPGA Prototyping Systems, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.

© 2015 Aldec, Inc. All rights reserved worldwide. Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.


Aldec, Inc.
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