52nd Design Automation Conference Designer Track Submission Site Opens

2015 tracks include front-end silicon design, back-end silicon design and embedded software and systems

LOUISVILLE, Colo. — (BUSINESS WIRE) — November 12, 2014The Design Automation Conference (DAC), the premier conference devoted to the design and automation of electronic systems, is pleased to announce the submission site for the 52nd DAC Designer Track is now open. The Designer Track brings together IC designers and embedded software developers from across the globe to present their design experiences on effective design flows, methods, and tool usage. The track offers a unique opportunity to network with and learn from other industry experts. The 52nd DAC will be held at the Moscone Convention Center in San Francisco, California, from June 7 - 11, 2015.

“The focus of the Designer Track is on the flows and methodologies deployed for ASIC design, verification, implementation and software integration by the user,” said Designer Track co-chairs Karam Chatha of Qualcomm Research and Daniel Bourke of Cadence Design Systems. “This track is the only one of its kind, developed exclusively by DAC to provide EDA tool users, hardware designers, software engineers, and application engineers the opportunity to share knowledge and experiences with each other. The covered topics are at the interface between design and automation, an area that until now has been under-represented in EDA.”

Submissions may describe the application of tools to the design of a novel electronic system or the integration of EDA tools within a design flow or methodology to produce such systems. A submission may be problem-specific in scope (e.g., hardware/software-based architecture exploration, analyzing substrate coupling during floorplanning) or may address a specific application domain (e.g., designing wireless handsets). The Designer Track differs from vendor-specific user forums in that it is not tied to a specific EDA vendor.

Designer Track

Regular submissions will be accepted in the following categories:

1.

   

Front-end silicon design (FE): Front-end architecture, design and verification of current day system-on-chip (SoC) including major components such as CPU, GPU, and DSP. Front-end design of entire SoC sub-systems such as graphics, multimedia and modem.

 

2.

Back-end silicon design (BE): Back-end design and verification of current day SoC, major sub-systems and constituent components (CPU, GPU and DSP). Relevant topics include (but are not limited to) physical design, clock tree generation, timing closure, verification, and design rule checking.

 

3.

Embedded software and systems (ESS): Compilers (CPU, GPU, DSP) and programming aids, parallelizing tools, test and verification, operating system (including RTOS), virtual platform, virtual machines and run time environments.

 

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