ASSET InterTech and Mentor Graphics IJTAG interoperability empowers two-way validation flow between chips and boards

Richardson, TX (Oct. 21, 2014 – International Test Conference, Seattle, WA, Booth 305) – Seamless interoperability between ASSET® InterTech ( and Mentor Graphics® Tessent® products for the IEEE P1687 Internal JTAG (IJTAG) embedded instrumentation standard will allow engineers to accurately debug and isolate issues in either a complex system-on-a-chip (SoC) or on the circuit board where the chip has been deployed. ASSET and Mentor are demonstrating IJTAG interoperability at the International Test Conference this week in Booths 304 and 305.

IJTAG resources, including embedded instruments and a network connecting them, are inserted into a chip with Mentor’s Tessent IJTAG solution. These instruments then allow engineers to verify and characterize the functionality and performance of the SoC at the chip level. When deployed on a circuit board, ASSET’s ScanWorks tool will be able to provide a debug loop by accessing IJTAG resources to isolate problems in both the SoC and the circuit board. Issues found at the chip level can be corrected before additional devices are fabricated.

“This two-way debug feedback between chip and board eliminates any doubt about whether the faulty behavior is in the chip or on the board,” said Al Crouch, vice chairman of the IEEE P1687 IJTAG working group and a chief technologist for ASSET. “Of course, conformance to the IEEE P1687 standard is critical to the interoperability between our ScanWorks tool and Mentor’s Tessent IJTAG solution. In my opinion, IJTAG will take a major step toward approval soon and once that happens, momentum will quickly increase for full industry adoption.”

“The complexity of today’s SoCs and the growing number of IP blocks integrated into these designs are making IJTAG a necessity if the industry is going to maintain its rapid pace of new product introductions,” said Stephen Pateras, Product Marketing Director at Mentor Graphics. “Aligning Tessent IJTAG with ASSET’s ScanWorks is a big step toward enabling our customers to fully capitalize on the potential of the IJTAG standard.”

IJTAG Workshop Series

“Our two companies, ASSET and Mentor, are committed to collaborating on several educational programs that will jump-start the adoption of IJTAG, including a series of workshops in major technology hubs in the U.S., Asia and Europe,” said Tim Caffee, ASSET’s vice president of design validation and test. “In addition, ASSET is publishing several IJTAG eBooks authored by Al Crouch, the vice chairman of the IJTAG working group. The early emergence of an IJTAG ecosystem of various tools will also help the adoption cycle.”

A series of IJTAG workshops is currently being planned by ASSET and Mentor for the spring of 2015. Attendance at one half-day session is reasonably priced at $295. Following the morning workshop, a limited number of private consultations will be available with the experts who will be teaching the workshop. For more information on the workshop series and a private consultation with the IJTAG experts, go to

About ASSET InterTech

ASSET InterTech is a leading supplier to the electronics industry of tools based on embedded instrumentation. Its SourcePoint debug and trace platform and the ScanWorks® platform for embedded instruments overcome the limitations of external test and measurement equipment. SourcePoint applies trace instrumentation embedded in code to debug software while ScanWorks applies instruments embedded in chips to test and validate chips and circuit boards during design and manufacturing. With ASSET’s software/hardware tools, engineers can quickly debug firmware and then diagnose how it interacts with hardware. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.

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