Digital Core Design, celebrating its 15th anniversary this year, has introduced the D68HC11K, which is a synthesizable soft IP Core Microcontroller, fully compatible with the Motorola MC68HC11K industry standard. It can be used as a direct replacement for the microcontrollers like: MC68HC11K0, MC68HC11K1, MC68HC11K4, MC68HC711K4, MC68HC11KS2 and MC68HC711KS2.
Bytom, Poland. October 1st 2014. In a standard configuration, the core has an integrated on-chip major peripheral functions. An asynchronous serial communication interface (SCI) and a separate synchronous serial peripheral interface (SPI) are included. The main 16-bit, free-running timer system, contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. – This and additional modes make the D68HC11K IP Core especially attractive for automotive and battery-driven applications – says Jacek Hanke, DCD’s CEO. Memory expansion unit (with six address extension lines) allows up to sixteen 32K byte banks of external memory to be addressed in either of two bank windows. The MEU extension of memory space can be up to 1MB. Self-monitoring, on-chip circuitry is included, to protect D68HC11K against system errors. To enable optima functionality in design, DCD’s IP Core implements eg:
- The Computer Operating Properly (COP) watchdog system, which protects against software failures
- An illegal opcode detection circuit provides a non-maskable interrupt, if illegal opcode is detected.
- Two software-controlled power-saving modes - WAIT and STOP avail to conserve additional power.
The D68HC11K Microcontroller Core can be equipped with the ADC Controller, which allows the usage of external ADC Controller with standard ADC software. This ADC Controller makes external ADC's visible in exact the same way as internal ADC's in original 68HC11K Microcontrollers.
DCD’s IP Core is fully customizable - it is delivered in the exact configuration, to meet users' requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.
And last but not least, to allow easy software debugging and validation, the D68HC11K has a built-in support for
DoCDTM - a
real-time hardware debugger, which provides debugging capability of
a whole System-on-Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers and SFRs, including user defined peripherals, data and program memories.
tel: + 48 32 282 82 66 ext.25,
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Digital Core Design, ul. Wroclawska 94, 41-902 Bytom, Poland
- Cycle compatible with original implementation
- Software compatible with 68HC11K industry standard
- I/O Wrapper, making it pin-compatible core
- SFR registers remapped to any 4KB memory page
- Two power saving modes: STOP, WAI
- Fully synthesizable
- Static synchronous design
- No internal tri-states
- Scan test ready
Information about Digital Core Design:
In 2014 Digital Core Design celebrates its 15th Anniversary. The company founded in 1999, since the beginning stands in the forefront of the IP Core market. High specialization and profound customer service enabled to introduce more than 70 different architectures. Among them is the world’s fastest 8051 IP Core, the DQ80251, which is more than 66 times faster than the standard solution. As an effect, over 300 hundred licensees have been sold to more than 500 companies worldwide. Among them are the biggest enterprises like e.g. Sony, Siemens, General Electric and Toyota. But a lot of DCD’s customers are small businesses, R&D laboratories or front/back end offices, which require exact solution tailored to their project needs. Rough estimations say that more than 250 000 000 devices around the globe have been based on Digital Core Design’s IP Cores.