Portfolio enables designers to take advantage of the higher performance, lower power and smaller area benefits of new advanced processSAN JOSE, Calif., Sept. 26, 2014 — (PRNewswire) — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced a broad portfolio of intellectual property (IP) for TSMC's 16nm FinFET Plus (16FF+) process. The wide array of IP for the 16FF+ process enables systems and semiconductor companies to take advantage of the 15 percent speed improvement with same total power or 30 percent total power reduction at the same speed compared to the16FF process.
Currently under development for the 16 FF+ process, the Cadence IP portfolio includes multiple high-speed protocols for several key memory, storage and interconnect standards critical in the development of advanced SoC designs. Silicon-tested IP is expected to be available beginning in Q4 2014. For detailed protocol information and availability details, customers should contact their local Cadence salesperson.
Cadence also announced today the qualification of its digital implementation, signoff and custom/analog design tools for the 16nm FinFET Plus process. Click here for more information.
"Our new 16nm FinFET Plus process is an important development for next-generation SoC designs as they balance the task of increasing performance while reducing power and area," said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. "As a long time trusted TSMC partner, we believe Cadence will play a vital role in the broad adoption of this new process with its certified tools and IP portfolio."
"Our broad portfolio of IP for 16 FinFET Plus will enable design teams to ramp quickly on next-generation SoC designs and immediately realize the performance and power benefits of this new FinFET process," stated Martin Lund, senior vice president and general manager of the IP Group at Cadence.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
This news release contains certain forward-looking statements, including expectations for technology and product development and introductions, technology and product capabilities, costs and performance and industry trends that are based on our current expectations and involve numerous risks and uncertainties that may cause these forward-looking statements to be inaccurate. This news release also contains forward-looking statements attributed to third parties, which reflect their expectations as of the date of issuance. Risks that may cause these forward-looking statements to be inaccurate include among others: Cadence's technology and products described in this press release may not be available when we expect or in the capacities that we expect or perform as expected, or the other risks detailed from time-to-time in our Securities and Exchange Commission filings and reports, including, but not limited to, our most recent quarterly report on Form 10-Q and our annual report on Form 10-K. We do not intend to update the information contained in this press release.
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