The Complete 'Full TCP and UDP stack' pre-ported and tested with their 6th generation industry leader '77 nanosecond TCP& UDP processing times and 95% TCP throughput,' Network Hardened, most reliable, mature and most widely adapted worldwide over the last 5 years.MILPITAS, Calif., July 2, 2014 — (PRNewswire) — Intilop, Inc. a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol Accelerators, Mega IP Cores, Systems and Solutions, has released a Xilinx Vertex 7 based development platform (INT_VC707) with pre-ported and tested 10G TCP & UDP Accelerators (TCP & UDP Full Offload Engines) which implement from 2 to 16 Thousand Simultaneous TCP & UDP Connections, unlimited continuous connections and Bandwidth of more than 1.1 Gigabyte/sec per port regardless of number of simultaneous or active TCP & UDP Sessions. In addition, it delivers the same hyper performance with same ultra-low latency (TCP/UDP) and Zero Jitter, irrespective of number of active connections.
The FPGA platform offers an 'Out of the box' working TCP & UDP hardware stacks with unprecedented functionality, ultra small core size, performance and flexibility. The Full TCP and UDP cores run without any CPU involvement. The TCP and UDP connections maintain the same high throughput and low latency/processing times regardless of number of simultaneous connections in progress. This is a vast difference compared with other leading TCP Accelerators that implement partial TCP Offloads and suffer major performance degradation when handling just 10 – 20 simultaneous TCP Sessions, not to speak of thousands of simultaneous TCP connections. The unprecedented TCP throughput of more than 95% for large and small size payload data transfers on a 10G network, which is 8 – 20x higher as compared to TCP/IP software running network traffic which is the de-facto standard.
In addition, the whole SOC subsystem containing PHY & EMAC & TOE & UOE, only takes up less than 12K Slices/26K LUTs and 4MB BRAM. It also integrates a DDR-III interface. The architectural innovation allows it to automatically switch to DDR when running thousands of TCP/UDP sessions. Customers can also use the DDR-III for their use as well. This allows customers to have maximum flexibility. They will be able to utilize smaller and less expensive FPGAs or ASIC technology to get all of the benefits of TCP/UDP hardware acceleration. A complete FPGA board/development Kit is delivered with pretested TOE/UOE subsystem which allows customers to start using it right away. It is expected to hasten the adaption of this technology in the vast array of next generation network connected devices. This new technology and platform offers many system level choices and flexibilities to customers in pretty much every vertical market who are building solutions for Hyper performance networking applications.
Their previous 5 generations of Full TCP Accelerators provide up to 256 Simultaneous TCP Connections and have also been available on the same FPGA platform.
A similar platform will be available with Altera FPGA devices in the near future.
As a pioneer, Intilop was the first company to deliver a series of Full TCP Offload Engines on FPGAs in 2009. Their sub 100 ns latency MAC+TOEs & UOEs are considered a 'Gold Standard' by the industry experts.
The latency barrier of sub 100 nanoseconds and throughput of more than 1 G byte/s per port had been set by them since their first 10G Series of TCP engines in 2011. And, now the same performance metrics are provided across all 16 Thousand Simultaneous TCP and UDP Sessions. A live demo is available upon request.
The highly deterministic performance, reliable and proven ultra-low latency, coupled with customizability offered by the 10G TOE & UOE is being effectively applied to gain wire-speed competitive edge by all Networking Equipment makers.
Customers now have a larger variety of cutting edge TCP offload products to choose from, when they want to move up in the nanosecond league from the microsecond league. By utilizing the full benefits of pivotal 10G UX TOE and UOE technologies they can confidently exceed their challenging network system performance objectives.
The TOE's Patent pending architecture is highly scalable, customizable and adaptable without compromising the low latency and performance. Intilop's product-line solutions are available in flexible FPGA/ASIC/SoC technologies which can easily accommodate diverse set of appliance maker's technical design specifications.
Intilop is a developer, recognized leader and pioneer in advanced networking silicon IP and system solutions, custom hardware solutions, SoC/ASIC/FPGA integrator and total system solutions provider for Networking, Network Security, storage and Embedded Systems.
Intilop Corporation. 830 N Hillview Drive. Milpitas, CA 95035. PH: 408-791-6700