Si2’s Low Power Coalition Releases Initial Specification Supporting Multi-Level Power Modeling

Defines Transaction Level Power Models

AUSTIN, Texas — (BUSINESS WIRE) — June 2, 2014 — Silicon Integration Initiative (Si2) today announced that the Low Power Coalition (LPC) has taken the first step toward a comprehensive approach to Multi-Level Power Modeling by approving the “Standards for Efficient System Level Power Analysis™” specification.

System level modeling has become increasingly widespread and important in the design of nanometer Systems-on-Chip (SoC). This increase has been driven by a variety of motivations including more efficient design representation, faster simulation speeds, and easier debugging among others. Unfortunately, system level power analysis and optimization has lagged behind other system level efforts in large part due to the lack of accurate and efficient high level power models.

Several reasons exist for the paucity of usable power models for system level design, not the least of which is that conventional power modeling capabilities fall short when attempting to accurately and efficiently model complex behavior. Additionally, no standards have been proposed to date for Transaction Level Power Models.

The specification describes the motivations, requirements, and semantics for accurately and efficiently creating and using Transaction Level Power Models for System Level Design. This new document is available from Si2 at: https://www.si2.org/openeda.si2.org/project/showfiles.php?group_id=76#p162.

“The collaborative development and approval of this transaction-level power modeling specification represents a bold step in tackling one of the most important emerging challenges facing SoC design teams,” said Steve Schulz, president and CEO, Si2. “The increasing market demands for reducing power consumption requires embracing Mobility markets in particular require greatly reduced levels of power consumption which mandates the development of new, higher-level design methodologies that must be matched with new power modeling semantics as provided by this specification.”

The Low Power Coalition is an open industry standardization group operating under the auspices of Si2. All interested parties are encouraged to join the LPC members and help them define standards for low-power design flows. For more information, see: http://www.si2.org/?page=726.

About the Low Power Coalition (LPC)

The Low-Power Coalition (LPC) is delivering enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. Member companies are: ANSYS (NASDAQ: ANSS), ARM (Nasdaq: ARMHY), Atrenta, Cadence Design Systems (Nasdaq: CDNS), Calypto Design Systems, Doecea Power, Entasys, IBM (NYSE: IBM), LSI (Nasdaq: AVGO), and STMicroelectronics (NYSE: STM).

About Si2

Si2 is the largest organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on the development and adoption of standards to improve the way integrated circuits are designed and manufactured, in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Now in its 26th year, Si2 is uniquely positioned to enable timely collaboration through dedicated staff and a strong implementation focus driven by its member companies. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world. www.si2.org

All trademarks are the property of their respective owners.



Contact:

Silicon Integration Initiative (Si2)
Bill Bayer, 512-342-2244 ext. 304




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