New Software From Plunify Solves FPGA Timing, Optimization Issues

SAN FRANCISCO, CA -- (Marketwired) -- Jun 02, 2014 -- The who's who of the chip design community will be in San Francisco this week for DAC, and new ideas, trends and technologies will be the talk of the show. Plunify, provider of a groundbreaking FPGA design application, will be on hand to join the conversations and offer a solution to some of the biggest challenges faced by FPGA designers today: meeting timing, reducing area and lowering power. At the show, Plunify will debut its new InTime software, which harnesses big data analytics to solve FPGA timing and optimization problems through machine learning -- without modifying code.

Used as a plugin to major FPGA tools, InTime is able to analyze an FPGA design and determine optimized strategies for synthesis and place-and-route. These strategies are derived from correlations between the design structure, types of FPGA resources used and the design constraints. InTime guides the design towards the specified timing, area or power performance goals. The sheer complexity and volume of data generated for every FPGA design makes it impractical for designers to analyze that data by hand, but InTime uses statistical methods and machine learning to draw insights from the data that can improve the quality of results. Additionally, InTime harnesses unused compute power to run builds -- and actively learns from build results to improve them over time.

According to Kirvy Teo, COO for Plunify, "InTime is incredibly intelligent -- InTime learns from previous build results and the more builds it does, the better the results become. InTime has the potential to be truly life-changing for FPGA designers -- enabling them to get better, faster results from the same FPGA software, without modifying their designs."

See for yourself -- Plunify invites DAC attendees to visit them at booth #209C on the show floor to get a firsthand look at InTime. To learn more, please visit, like them on Facebook or follow the company on Twitter.

About Plunify
Solutions from Plunify Pte. Ltd. enable semiconductor chip designers to shorten product time-to-market and reduce development costs -- with no disruption to existing workflows. The company's EDAxtend™ cloud platform and InTime™ timing closure tool help electronics companies meet FPGA design performance targets and significantly reduce their products' time to market. For more on Plunify's products, please visit

Image Available:

Media Contact:
Kevin Mayberry
Lages & Associates
(949) 453-8080

Email Contact 

Review Article Be the first to review this article
Autodesk - DelCAM

Featured Video
Jeff RoweJeff's MCAD Blogging
by Jeff Rowe
Apple Adding To Computer Product Line Minus Ports
Currently No Featured Jobs
Upcoming Events
3D Collaboration & Interoperability Congress at 1310 Washington Ave. Golden CO - Oct 25 - 26, 2016
Electric&Hybrid Aerospace Technology Symposium 2016 at Conference Centre East. Koelnmesse (East Entrance) Messeplatz 1 Cologne Germany - Nov 9 - 10, 2016
Autodesk University Las Vegas at Las Vegas NV - Nov 15 - 17, 2016
TurboCAD pro : Free Trial

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy Advertise