Cadence Offers Immediate Availability of DDR4 PHY IP on TSMC 16nm FinFET Process

SAN JOSE, Calif., May 19, 2014 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced immediate availability of DDR4 PHY IP (intellectual property) built on TSMC's 16nm FinFET process. The combination of 16nm technology and Cadence's innovative architecture helps customers realize the maximum performance of the DDR4 standard, which is specified to scale up to 3200Mbps, as compared to today's maximum of 2133Mbps for both DDR3 and DDR4 technologies. This technology enables server, network switching, storage fabric and other systems on chip (SoCs) requiring high-memory bandwidth to design-in Cadence® DDR4 PHY IP now and to exploit higher speed DRAMs when they become available.

Cadence Logo.

The Cadence DDR4 PHY IP supports an unbuffered dual in-line memory module (UDIMM)/ registered dual in-line memory module (RDIMM) with reliability, availability, and serviceability (RAS) features such as cyclic redundancy check (CRC) and data bus inversion (DBI). The new DDR4 PHY IP implements architectural innovations such as 4X clocking to minimize duty cycle distortion, multi-band power isolation for increased noise immunity, and I/O with slew rate control. The Cadence DDR4 PHY IP together with Cadence DDR4 controller are verified in silicon from TSMC's 16nm FinFET process.

"The demand for 16nm FinFET-based designs continues to grow and is driving the market need for a complementary DDR4 IP offering," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Because we have worked very early and closely with Cadence on this technology, our customers can review the design's silicon results to feel confident about turning to Cadence for comprehensive 16nm support from tools to IP."

"Many of our customers are concerned that their next-generation designs might not reach their performance goals because of the bottleneck in memory systems," stated Martin Lund, Cadence's senior vice president and general manager of the IP Group. "By using Cadence DDR4 IP, we believe our customers can have more confidence that their products will work with future DRAMs designed for higher speeds." 

DDR4 PHY IP is silicon-tested and available now. For more information on DDR IP, please visit http://ip.cadence.com/knowledgecenter/customize-main/ddr4-16ff

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.

© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Design Systems, Inc.
408-944-7039
Email Contact

Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com




Review Article Be the first to review this article

Featured Video
Editorial
Jeff RoweJeff's MCAD Blogging
by Jeff Rowe
Siemens Goes ECAD With Mentor Graphics Acquisition
Jobs
Mechanical Engineer for IDEX Corporation at West Jordan,, UT
GIS Analyst II for Air Worldwide at Boston, MA
Senior Structural Engineer for Design Everest at San Francisco, CA
Business Partner Manager for Cityworks - Azteca Systems, LLC at Sandy, UT
Upcoming Events
Design & Manufacturing, Feb 7 - 9, 2017 Anaheim Convention Center, Anaheim, CA at Anaheim Convention Center Anaheim CA - Feb 7 - 9, 2017
Innorobo 2017 at Docks de Paris Paris France - May 16 - 18, 2017
Display Week 2017 at Los Angeles Convention Center 1201 S Figueroa St Los Angeles CA - May 21 - 26, 2017



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy Advertise