Simulation of large netlists with thermal corners enabled
March 24, 2014 -- Grenoble -- Backend verification specialist EdXact SA today announces the availability of a new version of Jivaro-D, version 5.4. Jivaro-D allows to reduce the number of parasitics in post-layout extracted netlists, helping prominent simulation tools to lower the burden of those components. The result is that those simulation tools run faster, with a reduced memory memory footprint and the capability of handling larger netlists. Jivaro-D received a host of new features and new abilities.
Until version 5.2, Jivaro-D was dedicated to the reduction of passive components, such as resistors, capacitors, inductors, and controlled current and voltage sources. With version 5.3 EdXact introduced the reduction of active components, version 5.4 extends the capabilities by capabilities highly demanded by the user community.
The two most interesting additions are:
- Reduction of resistor elements containing thermal parameters. The simulation of thermal corners is important and the corners are typically determined inside the simulation tool. The existing reduction algorithms usually work at nominal temperature and could not keep the thermal parameters. The new algorithms allow to keep the thermal dependencies over the reduction process. The user can now reduce netlists and simulate thermal effects.
- Reduction of negative resistor elements. Advanced technologies nodes create the need for new modelling, sometimes by intentionally disrespecting the physical sense of network components available in spice simulation tools. One example is the support of double-biased gates, which are modelled with negative resistors. Those structures are now fully supported.
Jivaro-D is used for spice-based simulations of post-layout transistor- and gate-level netlists, which need to be carried out with good accuracy and therefore need to incorporate parasitic effects. Users of Jivaro generally use advanced technology nodes reaching from 90nm down to 14nm. Industrial applications are memory blocks, analog IPs, RF blocks, mixed-signal circuits, high-speed interfaces, ADC, image sensors and their interfaces and others.
Founded in 2004, EdXact SA focuses on electronic design tools aimed at physical verification tasks. EdXact’s innovative model order reduction technology helps to accelerate extensive backend verifications in complex IC design cycles. EdXact is headquartered in Grenoble area, France with sales offices in USA, Japan, Korea and Taiwan.
For additional information: http://www.edxact.com