EEPROM IP Core with configurable SPI parameters

Digital Core Design, IP Core and System on Chip design house from Poland introduced its latest solution – DEEPROM. It performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. Moreover, DCD’s IP Core DEEPROM implements configurable SPI parameters like serial clock prescaler, SPI mode, CS hold/setup.

Bytom, Poland. 3rd of February 2014 -- Digital Core Design, celebrating in 2014 its 15th anniversary introduced newest IP Core which targets DRAM designs. The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. Contents are accessible to the CPU in the same manner as a common SRAM memory, but require READY input to expand the time access. - Our proprietary core allows to map serial EEPROM in processor memory space and control it as the parallel memory – says JacekHanke, DCD’s CEO. The controller automatically sends all control instructions and read /write memory locations. As for the CPU, the EEPROM is being connected to it through the DEEPROM. Moreover, it's visible and controlled as parallel SRAM with long access time. – DEEPROM’s big advantage is that the core has been designed to operate with popular 25XXX SPI Serial EEPROMs from Atmel, Microchip – adds Hanke.

When all other factors are sustained, memory controller is becoming crucial. That's why DCD's IP Core has been developed to ensure the most accurate data flow. It was designed in accordance with JEDEC specification and all the other industry standards, which summarized together make the DEEPROM very small, efficient, with no internal tri-state buffers and signals IP Core.

More information: http://dcd.pl/ipcore/146/deeprom/

DEEPROM’s presentation: http://youtu.be/lHbSfQAerlM

DEEPROM’s Key Features:

ü  Standard memory interface with ready control

ü  Configurable SPI parameters

  • Serial clock prescaler
  • SPI mode
  • CS hold/setup

ü  Updating bits in EEPROM status register

ü  Simple interface allows easy connection to microcontrollers

ü  Fully synthesizable, static design with no internal tri-states

Information about Digital Core Design:

In 2014 Digital Core Design celebrates its 15th Anniversary. The company founded in 1999, since the beginning stands in the forefront of the IP Core market. High specialization and profound customer service enabled to introduce more than 70 different architectures. Among them is the world’s fastest 8051 IP Core, the DQ80251, which is more than 66 times faster than the standard solution. As an effect, over 300 hundred licensees have been sold to more than 500 companies worldwide. Among them are the biggest enterprises like e.g. Sony, Siemens, General Electric and Toyota. But a lot of DCD’s customers are small businesses, R&D laboratories or front/back end offices, which require exact solution tailored to their project needs. Rough estimations say that more than 250 000 000 devices around the globe have been based on Digital Core Design’s IP Cores.

 

Contact:

Tomeq Cwienk,
Digital Core Design
tel: + 48 32 282 82 66 ext.25,
skype: tomasz.cwienk,
mail to: Email Contact




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