Dolphin Integration launches new AHB compliant Cache controller to meet growing demand for both energy efficient and faster SoC with NVM

Grenoble, France. December 16, 2013 ---- With the goal of improving drastically the PPA mix (Power x Performance x Area) of Non Volatile Memories (NVM) like eFlash or EEPROM, Dolphin Integration announces today R-Stratus-LP, new generation of cache controller.

R-Stratus-LP provides advanced NVM based devices architecture with outstanding gains:

  • Power consumption of embedded or external NVM may be divided by 3X
  • Apparent frequency is accelerated by 3X

R-Stratus-LP is indeed the first L1 Cache Controller with an architecture optimized for Low-Power

  • Architecture designed to minimize the number of accesses to TAG and cache RAM and NVM memory
  • cache line size and associativity both runtime programmable on the fly

This cache controller has also been designed for facilitating its use by SoC integrators

  • Support of AHB-Lite interfaces to ensure easy integration within any MCU subsystem without need for any bridge
  • Separation of TAG and cache RAM memories from R-Stratus logic in order to ease portability across a wide range of process technologies.

For more information about this offering, have a look at the  presentation sheet

Our Application Engineer may help you appreciate fast the expectable improvements thanks to R-Stratus-LP cache controller based on your current NVM specification. Just  click here or contact  Email Contact for more information.




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