InCyte represents a step forward into optimization from Giga Scale IC's Time Architect(R) chip estimation product. It is used during the specify and create phases of IC design to capture specification, generate estimates, quotes and perform architectural and implementation optimization.
During chip creation, design teams want to optimize key elements, including logic and analog intellectual property (IP), embedded memory and repair, I/Os, power leakage and switching activity. Managers and architects need a quick, accurate method to compare and visualize various tradeoffs in library characteristics, semiconductor process nodes, memory configurations and IP.
InCyte includes a specification cockpit, estimation engine, floorplan generator, performance calculator and compare display, driven by a Giga Scale IC-proprietary Technology Macro Modeler (TMM). Bundled with a portfolio of libraries -- from 90nm to 0.35um -- and a broad family of hard and soft IP macros, users have a system with insight into available offerings from semiconductor vendors.
InCyte creates a Silicon Virtual Model(TM) (SVM) in industry standard process nodes or specific foundry/library vendor combination. It uses a graphical user interface (GUI) to replace spreadsheets for IC estimation. Users identify their target process nodes and libraries; define clock domains and voltage zones; select I/O pads and bonding styles; describe logic blocks; and select hard and soft IP. Since it's web-enabled, they can select from available libraries, memory compilers and hundreds of IP options optimized for their particular need and have updated information for the latest processes.
Introducing InCyte-Specify, InCyte-Create
InCyte-Specify(R), designed for estimation and architectural optimization, captures and optimizes the initial chip specification. Creation of an optimized SVM model often requires extensive research into available IP, behavior of various libraries, leakage, power and performance analysis and the impact of memory on yield. InCyte-Specify is bundled with data needed to create the specification, as well as the ability to optimize architectures. Its visualization capability displays tradeoffs between conflicting requirements of die size, memory yield, total power, leakage and cost. Users can find specific architectural problems while gaining confidence that their IP and library choices will meet their goals.
InCyte-Create(R) is targeted to a design team's chip creation and implementation process and provides a means of seeing the impact of design changes without having to implement them through to backend design. It allows users to add details to the IC's model and its blocks and vary key assumptions in minutes without requiring backend design. Providing a "chip and block optimizer" means teams can have insight into available tradeoffs in switching activity, memory performance, yield and IP alternatives.
Bundled with data feeds, it acts as an information portal for disaggregated semiconductor information on the targeted foundry and library. TMM data models let InCyte-Create be used as a power optimization system at the block or chip level.
Meant for design teams who have selected a foundry or application specific integrated circuit (ASIC) vendor, InCyte-Create improves information flow between customers and application engineers at their suppliers.
Teams implementing a design perform continual tradeoff analysis. With today's EDA tools, tradeoffs are laborious, time consuming and expensive. InCyte-Create provides the ability to "seed" initial chip estimation into commercial floorplanners through LEF/DEF or custom interfaces. Designers can see how the layout is intended at the start of the project and prior to having any electronic design automation (EDA) data to implement. Register transfer level (RTL) estimation, via an optional RTL Calculator or as synthesis proceeds, can revalidate assumptions on soft IP or its implementation.
With InCyte-Create, multiple memory parameters -- speed, aspect ratio, size, power and test -- can be varied quickly. The large set of IP offerings can be used to evaluate partitioning memories or different voltage thresholds. InCyte-Create works with design teams to optimize and re-verify the initial architecture and assumptions. Its performance calculator displays flip-flop, stage and transport (wire) delays, allowing different library options to be used in a block.
Additional features common to both InCyte products include leakage modeling, performance calculation, embedded memory selection, test and repair, built-in self test (BIST) and scan modeling, and several user level controls over implementation details. It has an Excel import capability for IP and IC specifications and a checkout feature for data to flow into standard EDA software. While the majority of designs today are IP based, RTL designs are still significant. InCyte's RTL Calculator can read Verilog and VHDL and compute estimates without the need to own or run a synthesis tool. This addresses the need to evaluate RTL code from a previous design in a new technology, as well as the ability to update estimates as RTL development proceeds.
InCyte-Specify lets architects enter a design with a ready-to-use system and experiment with design concepts in minutes because Giga Scale IC's new generic server includes models of industry average processes from 90nm to 0.35um. It provides an economical way to evaluate a chip concept and select a particular process node and available IP.
Data is based on industry averages collated from various library and IP data, and estimates are expected to be within 10-15 percent of actual figures. Once a concept is validated, users can then map the same design onto a "branded" server that provides more detailed foundry, library and IP data.
Both tools access these "branded" servers, based on vendor design kits from various foundry and library vendors, for specification and optimization. Users can further optimize the SVM within a process node and see results across process variants -- 0.13um Low-K, 0.13um LowV-LowK-Overdrive, 90nm HighVt, for example.
The ability to map a specification onto available choices allows the entire design space to be explored and architectural tradeoffs to be made, resolving conflicting goals of low leakage, high speed, lower total power and smallest die size.
Expanded offerings from Artisan Components, Inc. (Nasdaq: ARTI) and Virage Logic Corporation (Nasdaq: VIRL) are available with both products. InCyte servers contain more than 130 library variants and 115 memory compilers currently supporting Taiwan Semiconductor Manufacturing Company (TSMC) (NYSE: TSM) and UMC (TAIEX: 2303, NYSE: UMC).
InCyte offers online documentation, tutorials and an e-commerce website where users can evaluate and purchase access to InCyte and its Data Servers.
The InCyte product family will be demonstrated at the 41st Design Automation Conference (DAC) in Booth Number 4339 from Monday, June 7, through Wednesday, June 9, at the San Diego Convention Center in San Diego, Calif.
Pricing and Availability
The InCyte product family is available now, and runs on Windows, Sun, Linux, or Mac OS X machine. Pricing for InCyte-Specify is $1,500 per month or $6,000 per year for a single user with access to the generic server. InCyte-Create is priced from $15,000 per year and can be purchased as a perpetual or a time-based license.
For more information, contact Arklin Kee, vice president of sales and business development at Giga Scale IC. He can be reached at (408) 255-0444, Ext. 302, or via email at firstname.lastname@example.org.
About Giga Scale IC
Founded in 2003, Giga Scale Integration Corporation -- or Giga Scale IC(TM) -- is a private Electronic Design Automation (EDA) software company that develops InCyte(R), the first Specification Optimization System for integrated circuit (IC) design. Used during the Specify and Create phases of design, InCyte generates a Silicon Virtual Model(TM) (SVM) containing power, leakage, speed, die size, yield and cost for different processes. InCyte includes a specification cockpit, floorplanner and estimator bundled with semiconductor intellectual property (IP) to create the SVM. The SVM interfaces with other EDA tools and is used across the semiconductor supply chain to ensure compliance with the specification. Giga Scale IC corporate headquarters are located at: 10050 North Wolfe Road, Suite SW1-266, Cupertino, Calif. 95014. Telephone: (408) 255-0444. Facsimile: (408) 255-0344. Email: email@example.com. Web Site: http://www.gigaic.com.
Note to editors: Gary Smith of Dataquest has been briefed and is available for comment. He can be reached at: (408) 468-8271 or firstname.lastname@example.org.
InCyte, InCyte-Specify, InCyte-Create and Time Architect are registered trademarks of Giga Scale Integration Corporation. Giga Scale IC, First Tool in the Design Chain and Silicon Virtual Model are trademarks of Giga Scale Integration Corporation. Giga Scale IC acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Public Relations for Giga Scale IC Nanette Collins, 617-437-1822 Email Contact