Mentor Graphics Tools Included in TSMC’s 3D-IC Reference Flow for True 3D Stacking Integration

Expands support for interposer- and TSV-based physical design, verification, extraction, thermal and testing to full 3D

WILSONVILLE, Ore. — (BUSINESS WIRE) — September 19, 2013Mentor Graphics Corp. (NASDAQ: MENT) today announced that its solutions have been validated by TSMC with a true 3D stacking test vehicle for TSMC’s 3D-IC Reference Flow. The flow expands support from silicon interposer offerings to include TSV-based, stacked die designs. Specific Mentor® offerings include capabilities for metal routing and bump implementation, multi-chip physical verification and connectivity checking, chip interface and TSV parasitics extraction, thermal simulation, and comprehensive pre- and post-package testing.

The Mentor Graphics® 3D-IC flow for TSMC provides a rich set of enhancements across the Mentor IC product portfolio. The Olympus-SoC™ place and route system serves as the 3D-IC physical design cockpit for both silicon interposer- and TSV-based designs with support for cross-die bump mapping and checking; TSV, microbump, and backside metal routing; and copper pillar bump implementations.

The Pyxis® IC Station custom layout product provides schematic-driven layout that supports a TSV design flow. It also enables both orthogonal and 45 degree redistribution layer (RDL) routing. Specific enhancements for the TSMC 3D-IC flow include improvements to the bump file import process.

Whether the designer is working in a custom or digital design cockpit, the Calibre® nmDRC™ and Calibre nmLVS™ products provide inter-die design rule and layout vs. schematic checking, including IO alignment accuracy verification, and connectivity checking for double-sided bumps using either DEF or GDS input. The Calibre xRC™ and Calibre xACT™ products extract parasitics for backside routing and single- or double-sided bumps defined in DEF or GDS formats. They also handle TSV-to-TSV coupling extraction to drive static timing analysis and SPICE simulations, and generate TSV sub-circuit equivalents for multi-die parasitic models.

In the test area, the Mentor Tessent® MemoryBIST product supports testing of stacked Wide IO DRAM die, while Tessent TestKompress® provides die-to-stack level test pattern translations for both compressed and uncompressed test patterns. Tessent IJTAG also supports 3D interconnect tests for dies wrapped with IEEE 1149.1 and 1500 style wrappers.

To address the thermal issues inherent in 3D-IC designs, the Mentor FloTHERM® product provides both static and transient thermal models for dies and 3D assemblies, and works with the Calibre RVE™ and Calibre DESIGNrev™ products to provide die and package level temperature visualizations.

“Deep collaboration with Mentor in 3D-IC has resulted in a comprehensive solution for our mutual customers,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Extending Mentor products to cover true 3D stacking gives our customers flexibility to choose among different scaling alternatives, and a smooth transition between approaches.”

“It paves the way for our customers to access 3D-IC technology with comprehensive support of a full 3D-IC flow from physical design through thermal analysis, verification, extraction, and test without major disruption to their existing development process,” said Joseph Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “The designer’s approach to scaling can remain focused on performance and cost targets, without the risk of unfamiliar methods and tools.”

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year of nearly $1,090 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

(Mentor Graphics, Mentor, Calibre, Pyxis, FloTHERM, Tessent and TestKompress are registered trademarks and Olympus-SoC, nmDRC, nmLVS, xRC, RVE, DESIGNrev and xACT are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)



Contact:

Mentor Graphics
Gene Forte, 503-685-1193
Email Contact
or
Sonia Harrison, 503-685-1165
Email Contact




Review Article Be the first to review this article
HP

Autodesk - DelCAM

Featured Video
Jobs
Principal Research Mechatronics Engineer for Verb Surgical at Mountain View, CA
Senior Mechanical Engineer for Verb Surgical at Mountain View, CA
CAD Systems Administrator for KLA-Tencor at Milpitas, CA
Industrial Designer Intern – Spring 2017 for Nvidia at Santa Clara, CA
Lead Geospatial Analyst for Alion at McLean, VA
Upcoming Events
PI APPAREL Hong Kong 2017 at SHANGRI-LA KOWLOON 64 Mody Road Tsim Sha Tsui East Kowloon Hong Kong - Apr 5 - 6, 2017
SOLIDWORKS intro and hands on session – Slough at Baylis House, Slough, Berkshire, SL1 3PB Slough United Kingdom - Apr 7, 2017
PMTS 2017 at Greater Columbus Convention Center Exhibit Halls E, F, & D 400 North High St. Columbus OH - Apr 25 - 27, 2017
Engineer 3D! Training + Technology Conference at Hyatt Regency Milwaukee 333 West Kilbourn Avenue Milwaukee WI - Apr 25 - 26, 2017
MasterCAM



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy Advertise