Cadence and ARM have collaborated on the design and verification of high-performance SoCs and Systems using an optimized solution of tools and methodologies from Cadence with processors and physical IP from ARM. These will be featured during paper presentations and sponsored sessions during the event.
Find out how the collaboration between Cadence and ARM is enabling customers to build revolutionary electronics products -- faster and with greater confidence of first-pass success.
Santa Clara Convention Center
5001 Great America Parkway, Santa Clara, Calif.
October 30 - November 1, 2012 - 8:15 a.m. to 6:15 p.m.
Day 1 - October 30, 2012
Cadence Booth #36 Demonstrations
- RTL-to-GDSII flow for ARM Cortex-A processors
- Embedded Cortex-M0 system verification
Sponsored Sessions - Room #204
10:30 - 11:20
Automating the verification of SoC interconnect fabrics
Huzaifa Dalal, Senior Product Marketing Manager - VIP, Cadence and Mirit Fromovich, Staff Solutions Engineer, Cadence
11:30 - 12:20
Power efficient big.LITTLE processing: lessons learned from a 28nm multi-core Cortex-A7 low-power implementation
Paddy Mamtora, Group Director, Cadence
1:00 - 1:50
Designing with 14nm FinFET Technology
Lars Liebman, STSM, Distinguished Engineer, Design-Technology Co-Optimization, IBM
Vassilios Gerousis, Distinguished Engineer, Cadence
2:10 - 3:00
Implementing Advanced Next Generation Mali T6XX GPUs with Cadence Encounter Digital Flows
Sanjiv Taneja, Vice President, Research and Development, Cadence
3:10 - 4:00
Designing mixed-signal with ARM Cortex-M0
Sathishkumar Balasubramanian, Senior Technical Marketing Manager
4:10 - 5:00
Optimizing Power Efficiency in GHz+ Quad-core ARM Cortex-A15 Processor Hardening
Paddy Mamtora, Group Director, Cadence and Ashutosh Majumdar, ARM
- ATC-101 Tues @ 10:30am
Silicon Validation of GLOBALFOUNDRIES-Cadence Digital Design Flow in 28nm using ARM Physical IP
- ATC-103 Tues @ 10:30am
Advantages of NVMe for Low-Power Storage - Tom Hackett
- ATC-106 Tues @ 11:30am
Building Your UVM Environment for ACE-Based Verification - Mirit Fromovich, Tamar Meshulum
- ATC-112 Tues @ 2:10pm
A Novel Power Intent Specification Methodology for the IP Developer - John Decker
- ATC-110 Tues @ 2:10pm
Cache-Coherent Interconnect Complexity, Verification, and Performance Analysis - Nick Heaton, Stewart Penman, Paul Martin (ARM)
- ATC-117 Tues @ 3:10pm
Improving Performance, Power, and Area of a High-Speed Dual-Core ARM Cortex-A9-Based SoC with Clock Concurrent Optimization Technology - Koen Lampaert (Broadcom), Jason Corbisiero
- ATC-123 Tues @ 4:10pm
PCIe Gen 3 Implementation on AXI - Ashwin Matta
Days 2 and 3: System and Software Design Conference - October 31 and November 1, 2012
Cadence Booth #417 Demonstrations
- Cadence System Development Suite
- Power-Aware Signal Integrity Analysis
Sponsored Session - Room #212; Wednesday, October 31, 11:30am - 12:30pm
Prototyping and Early Software Development for ARM-Based Embedded Systems
This session will show available prototyping options and how each can benefit hardware and software teams. Discover the benefits of using a set of connected engines that enable hardware/software co-development and verification, from virtual prototyping through RTL simulation, acceleration, and emulation to FPGA-based prototyping. Also see a detailed analysis of hybrid use models that combine RTL executed in emulation with transaction-level models running in virtual prototyping, connected through transactors, built from Accelerated Verification IP (AVIP).
- ATC-218 Wed @ 2:30pm
Improving the Speed and Debug Ability of the Emulation/Prototyping Phase of ARM SoC Development - Leonard Drucker
- ATC-303 Thurs @ 10:30am
Analysis of Software-Driven Power-Management Policies using Functional Virtual Platforms - Michele Petracca
- ATC-323 Thurs @ 10:30 Fast-Track To Embedded Design With ARM Cortex-M0+ And Cadence Mixed-Signal IC Design Flow - Thomas Ensergueix (ARM), Mladen Nizic
For a complete description of Cadence activities at ARM TechCon 2012, visit the Cadence Web site.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
For more information, please contact: Nancy Szymanski Cadence Design Systems, Inc. Email Contact 415.420.5008 mobile