PLDA Introduces QuickUDP – 10G UDP Hardware Stack IP for FPGA

The PLDA QuickUDP IP delivers extremely low latency and high performance, with a standardized user interface that enables seamless integration into FPGA designs

SAN JOSE, Calif. — (BUSINESS WIRE) — October 17, 2012 — PLDA, the industry leader in interconnect IP, today unveiled its 10Gb UDP Hardware stack IP core. PLDA’s QuickUDP IP solution is a 100% RTL-designed IP, compliant with the IEEE802.3 specification and supporting the ARP, IPv4, ICMP, IGMP, and UDP protocols.

QuickUDP features full RTL Layers 2, 3, 4 implementation with integrated 10G Ethernet MAC, and an integrated Layer 1 XGMII PHY interface. The IP supports up to 256 UDP connections with an easy-to-use Avalon-ST or AMBA AXI4 user interface that enables instant integration into either Altera-based or Xilinx-based FPGA designs.

PLDA QuickUDP Key Features at a glance:

  • Management of layers 1, 2, 3 and 4 (OSI Model), compliant with:
    • Layer 1: IEEE802.3
    • Layer 2: IEEE802.3, ARP (Address Resolution Protocol)
    • Layer 3: IPv4, IGMP v2, and ICMP (Internet Control Message Protocol)
    • Layer 4: UDP
  • UDP management with up to 256 connections in each direction
  • MTU (Maximum Transmission Unit) up to 9000 bytes payload for supporting Standard and Jumbo Ethernet frames
  • Hardened ICMP Client and ARP Server/Client
  • VLAN configurable at runtime
  • Supports Unicast and Multicast transmit/receive
  • Supports IGMP v2 Membership Report/Leave
  • Avalon Streams user interface for data: 64-bit wide interface running at 156.25-MHz for UDP client port or 64-bit wide interface running at 156.25-MHz for MAC client port (UDP bypass)
  • PHY interface with XGMII interface to integrated XAUI PHY or 10G PMA-PCS
  • PHY/SFP management including MDIO (Management Data I/O) master controller for External 10G transceiver management or I2C (Inter Integrated Circuit) master controller for QSFP/SFP module management and 32-bit AXI4Lite slave control interface for MAC, UDP configuration and MDIO/I2C access

“The PLDA QuickUDP IP core joins our QuickPCIe and QuickTCP IP cores to create the industry’s most robust offering of high performance, low latency interconnect solutions,” said Stephane Hauradou, CTO for PLDA. “These IP offerings underscore our commitment of providing exceptional IP with remarkable ease of integration to our 2000+ clients worldwide.”

Availability and evaluation:

The PLDA QuickUDP IP is available now from PLDA. For a risk-free, free of charge evaluation, visit www.plda.com.

About PLDA

PLDA is a leading provider of semiconductor intellectual property (IP) specializing in high-speed interconnect protocols and technologies. PLDA is headquartered in Aix-en-Provence, France, and has a strong worldwide presence with a North American sales and technical support office in San Jose, California and a worldwide distribution network. For more information visit www.plda.com.

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Contact:

For media inquiries and more information, please contact:
PLDA
Michelle Tang, 408-273-4528
Email Contact




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