STATS ChipPAC Advances Through Silicon Via Capabilities With the Qualification of 300mm Mid-End Processing and Low Volume Manufacturing

SINGAPORE--28/08/2012, UNITED STATES -- (Marketwire) -- Aug 27, 2012 -- STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (SGX-ST: STATSChP), a leading semiconductor test and advanced packaging service provider, today announced that its Through Silicon Via (TSV) capabilities have achieved a new milestone with the qualification of its 300mm mid-end manufacturing operation and transition to low volume manufacturing.

STATS ChipPAC is firmly engaged with multiple strategic customers on TSV development programs which support the semiconductor industry's shift to 2.5D and 3D packaging integration for the mobile, wireless connectivity and networking market segments. The Company's current 3D TSV development and customer qualification activities include devices at the 28nm silicon node, application processors (AP) and graphic processors utilizing TSV for the high performance wide input/output (Wide I/O) memory interface required by higher bandwidth applications for the mobile market.

STATS ChipPAC was one of the first Outsourced Semiconductor Assembly and Test (OSAT) providers to invest in back-end of line (BEOL) manufacturing capabilities for 2.5D and 3D TSV technology on 200mm wafers. The Company's BEOL services include chip-to-chip and chip-to-wafer assembly with stealth dicing and fine pitch micro-bump bonding down to 40um. Since April 2011, STATS ChipPAC has been rapidly expanding its TSV offering with 300mm mid-end of line (MEOL) processing capabilities.

"The need for higher levels of integration, improved electrical performance, reduced power consumption, faster speed, smaller device sizes and shorter interconnects is forcing a shift to more complex 2.5D and 3D package designs utilizing TSV technology. TSV technology will be a key requirement in the convergence of mobile communication and computing functionality in devices such as smartphones and tablets. This is a trend which is expected to drive rapid growth and adoption of TSV technology," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.

The mid-end TSV process flow occurs between the wafer fabrication and back-end assembly process supporting the advanced manufacturing requirements of 2.5D and 3D packaging including wafer level, flip chip and embedded technologies. STATS ChipPAC's MEOL assembly services include microbump technology down to 40um, temporary bond/de-bonding, backside via reveal, isolation and metallization. With the early development of its MEOL capability, STATS ChipPAC is well positioned to support the increasingly popular industry model for 2.5D/3D integration of disparate silicon devices at the package level by an OSAT provider.

Dr. Han continued, "During the implementation phase of our mid-end TSV operation, we investigated multiple process options and identified key cost variables that would affect the commercialization of this technology. Our primary focus has been to develop high volume TSV technology capabilities that we can offer to customers at cost points that make TSV a viable solution. We now have mid-end manufacturing capacity in place in Singapore and are actively engaged with multiple strategic customers on the production qualification of 2.5D and 3D packaging designs."

Forward-Looking Statements
Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, the timing and impact of the expected closure of the Thailand Plant as well as the estimated associated cost for the closure; the amount of the property damage and business interruption insurance claim due to flooding of the Thailand Plant; the ability to shift production to other manufacturing locations, shortages in supply of key components and disruption in supply chain; general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilisation; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; classification of our Company as a passive foreign investment company; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited ("Temasek") that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labour union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; the continued trading and listing of our ordinary shares on the Singapore Exchange Securities Trading Limited ("SGX-ST"). You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.

About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices in 10 different countries. STATS ChipPAC is listed on the SGX-ST. Further information is available at Information contained in this website does not constitute a part of this release.

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