Then, on July 10 and 24, 2012, the U.S. Patent and Trademark Office (USPTO) issued more DFT related patents (U.S. Patent No. 8,219,945 and 8,230,282) to SynTest. SynTest now has a very broad portfolio of DFT patents in the Scan Compression and Logic BIST areas, notably U.S. Patent Nos. 7,412,637, 7,412,672, 7,552,373, 7,721,172, and 7,590,905 (for conventional scan compression), 7,512,851 (for low-pin-count scan compression), 7,945,833 (for pipelined scan compression), and 7,007,213, 7,260,756, and 7,779,323 (for logic BIST).
"To date, StarDFX and SynTest have been issued 37 US patents, and I am particularly excited about StarDFX's proprietary robust scan technology covered by this patent because it opens up a new important field in Design-for-Reliability (DFR) for the semiconductor industry and for StarDFX," said Dr. L.-T. Wang, Founder, President and CEO of StarDFX and SynTest. "The patented robust scan cells, referred to as Configurable Soft-Error Resilience (CSER) cells, combined with user-preferred Soft-Error-Rate (SER) mitigation cells and the associated RobustScan product from StarDFX can be linked to third-party scan synthesis and SER analysis programs and are fully compatible with SynTest's DFT products for test, debug, and diagnosis."
"Effective soft-error protection mechanisms are not just needed for technology nodes below 65 nm, users of enterprise servers and networking hardware readily demand limits on SER. StarDFX and SynTest customers in the automotive, aerospace, medical, and networking industry will now benefit from the availability of the soft-error protection framework offered by RobustScan," added Dr. Ravi Apte, VP of Strategy, Marketing and Business Development of SynTest.
StarDFX Technologies, Inc., established in 2009, develops advanced Design-for-Excellence (DFX) IPs and tools (including Logic BIST, Concurrent Fault Simulation, and Logic Reliability) and markets them, through SynTest as its sales channel, worldwide to semiconductor companies, system houses, and design service providers.
SynTest Technologies, Inc., established in 1990, develops advanced Design-for-Test (DFT) and Design-for-Debug/Diagnosis (DFD) IPs and tools (including Memory BIST, Boundary-Scan Synthesis, Scan/ATPG with Test Compression, and Silicon Debug and Diagnosis) and markets them worldwide to semiconductor companies, system houses, and design service providers. SynTest products improve an electronic design's quality and reduce overall design and test costs. SynTest is headquartered in Sunnyvale, California, and has field offices in Taiwan and China, and distributors in Europe, Japan, Korea, and Israel. More information regarding SynTest is available at www.syntest.com.
SynTest Technologies, Inc.
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© SynTest Technologies, Inc. 2012. All Rights Reserved. SynTest and RobustScan are trademarks of SynTest Technologies, Inc. All other trademarks are property of their respective owners.
Press Contact: Ravi Apte 408-720-9956 x 300