Aldec at DAC 2012: 10 Face-to-Face Sessions

HENDERSON, Nev. — (BUSINESS WIRE) — May 23, 2012Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions, will bring its top engineers to meet one-on-one with attendees at the industry’s annual Design Automation Conference ( DAC). This year, DAC runs June 3-7, 2012 at the Moscone Center in San Francisco, California.

Aldec offers convenient pre-registration for Technical Sessions: Registrations confirmed to date indicate the top trending Aldec sessions at DAC are:


Simulation on the Cloud: Unlimited Possibilities

Aldec has enabled running RTL and Timing simulation on the secured cloud, providing access to a virtually unlimited number of high performance servers.

UVM in Aldec Tools: Verification and Debugging

Aldec’s support of the latest UVM library, graphical debugging features to help designers find and fix issues more efficiently, and exciting future enhancements coming later this year.

High-Level VHDL Verification Doing Well with Help of New OS-VVM Community

Aldec, an early OS-VVM supporter, is hosting an open OS-VVM User Group Meeting on Monday, June 4, 2012 at 2:00pm in Booth #2126.


Achieve 10+ MHz Emulation of 100 Million ASIC Gates with True RTL Debugging ; Hardware and Software design teams can also now Use Virtual Platforms with Transaction Level Emulation .


Other popular Aldec sessions include:

Requirements-based FPGA Testing Method for DO-254

Early Validation of Custom IP for Zynq-based Designs

Interoperable IP Encryption (P1735): Safe and Smooth Multi-vendor Encryption Flow

A Highly Productive, Integrated Analog Mixed-Signal (A/MS) Solution from Tanner EDA

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