Software Demos in Booth #1514 Include AWR 2011 Product Portfolio, Analyst™ 3D FEM EM Debut; AWR and Partners MicroApps; and Annual Customer Party
EL SEGUNDO, Calif. — (BUSINESS WIRE) — May 15, 2012 — AWR Corporation, the innovation leader in high-frequency EDA software, once again takes a leadership position at the International Microwave Symposium (IMS) 2012 with a full slate of AWR 2011 software demonstrations, MicroApps presentations and panel, and its renowned Customer Appreciation Party.
IMS 2012 takes place from June 17 to 22 in Montréal, Canada.
Visit AWR at Booth #1514 to see Analyst 2012, AWR’s 3D FEM EM technology for bumps, bond wires, tapered vias and more, as well as the latest release of Microwave Office™, Visual System Simulator™ (VSS), AXIEM® and Analog Office® for MMIC, RFIC, RF PCBs and module design.
AWR software demonstrations:
Analyst 2012 debut:
- 3D FEM EM for bond wires, bumps, balls, ribbons, tapered vias, finite dielectrics
AWR 2011 product line including recent additions of:
- VSS and LabVIEW co-simulation for signal processing, hardware in the loop, and communications standards like LTE and 802.11ac
- VSS’s Radar Library, Frequency Planner and more
- Microwave Office/AXIEM and CapeSym for electrical-thermal MMIC co-simulation
- Microwave Office/AXIEM for PCB verification via ODB++
- AXIEM’s 3D antenna plots
AWR and its partners will be presenting 11 MicroApps and participating on a panel at the MicroApps Theater (Booth #1223). These talks provide additional insight into novel applications for and technologies within AWR software.
Tuesday, June 19:
|12:50 p.m.||Fully Integrating 3D Electromagnetic (EM) Simulation into Circuit Simulation|
Wednesday, June 20:
|9:05 a.m.||RF Link Prediction - A New and Novel Approach|
|10:50 a.m.||Linking RF Design through to Test|
Panel Session: Device Characterization Methods and Advanced RF/Microwave Design, details are available at http://goo.gl/x2RNw
|3:30 p.m.||RF System Design -- Moving Beyond a Linear Datasheet|
|3:35 p.m.||Improve Microwave Circuit Design Flow through Passive Model Yield and Sensitivity Analysis|
|4:35 p.m.||Electrical/Thermal Coupled Solutions for Flip Chip Designs|
|4:50 p.m.||System Simulation Featuring Signal Processing Blocks|
Thursday, June 21:
|11:20 a.m.||Optimizing the Design and Verification of 4G RF Power Amplifiers|
|11:35 a.m.||Simulating an NXP Doherty Power Amplifier with Digital Pre-Distortion|
|12:50 p.m.||Practical Electromagnetic Modeling of Parallel Plate Capacitors at High Frequency|
|1:20 p.m.||Use of FPGAs for Faster Test Times and Repeatability on Cellular Measurements|
|1:50 p.m.||Mind Your Reference Plane|