Cadence to Showcase Advanced Verification at DVCon 2012

SAN JOSE, CA -- (MARKET WIRE) -- Feb 22, 2012 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, will showcase its advanced verification technologies and methodologies at DVCon 2012.

WHEN: Feb. 27 to March 1

WHERE: DoubleTree Hotel, San Jose

WHAT: Cadence will demonstrate its technology, deliver papers and participate in tutorials and a panel discussion throughout the four-day DVCon 2012, a leading trade show focused on verification. Cadence experts will be available at Booth #1102 to discuss the latest technologies and methodologies.

Members of the Cadence team will participate in:


  • Accellera-Sponsored Tutorials
    • Feb. 27 -- Extending Fixed Subsystems at the TLM Level -- Experiences from the FPGA World
    • Feb. 27 -- UVM: Ready, Set, Deploy
    • Feb. 27 -- Introduction to Unified Coverage Interoperability Standard
    • March 1 -- Using Apps to Take Formal Analysis Mainstream

  • Cadence-Sponsored Lunch Tutorial: Earn Your Degree in the Low-Power Arts and Sciences, Feb. 28

  • Panel: Build or Buy: Which is the Best Practice for Hardware-assisted Verification? Feb. 29

  • Conference papers: Feb. 28
    • 131-WH864: The Case for Low-Power Simulation-to-Implementation Equivalence Checking -- Cadence
    • 131-TO356: Register This! Experiences Applying UVM Registers -- Cadence
    • 131-PD272: Hardware/Software co-verification using Specman and SystemC with TLM ports -- PMC-Sierra
    • 131-ZS887: Yikes! Why is My SystemVerilog Testbench So Slooooow? Cadence with IBM
    • 131-HW244: Shaping Formal Traces without Constraints: A Case Study in Closing Code Coverage on a Crypto Engine using Formal Verification -- Ubicorn
    • 131-VI576: From Spec to Verification Closure: a case study of applying UVM-MS for first pass success to a complex Mixed-Signal SoC design -- Maxim

  • Conference papers: Feb. 29
    • 131-UE177: Memory Debugging of Virtual Platforms with TLM 2.0 -- Cadence
    • 131-CS172: Bringing Continuous Domain into SystemVerilog Covergroups -- Cadence

  • Booth demos including low-power verification with UVM SystemVerilog, simplified coverage visualization and management, verification IP, and FPGA-based prototyping.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc., in the United States and other countries. All other marks and names are the property of their respective owners


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For more information, please contact:
Dean Solov
Cadence Design Systems

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