HENDERSON, Nev. — (BUSINESS WIRE) — January 9, 2012 — Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM™), underscoring the partnership’s commitment to provide continued support to the VHDL design community. OS-VVM delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, providing advanced features to VHDL design engineers while enabling them to continue to develop using VHDL.
“Hardware description languages such as VHDL and Verilog have provided electronics design engineers the ability to create complex digital projects. However, the challenge that many designers face is how to support system-level design requirements.” said Igor Tsapenko, Aldec Director of Engineering, “In recent years, new language standards such as SystemVerilog and SystemC have emerged to aid in performing advanced system verification tasks, leaving VHDL designers with the dilemma of learning a new language.”
Jim Lewis, Director of VHDL Training at SynthWorks, adds, “The unique feature of OS-VVM is the ability to use live results of Functional Coverage to control randomization of stimulus. This ‘intelligent coverage’ helps minimize the number of test cases that need to be generated to achieve complete coverage - resulting in fewer simulation cycles and a higher velocity of verification.”
Benefits of OS-VVM
- It provides access to advanced randomization and functional coverage capabilities (previously available only within system-level methodologies) that can be used in any testbench;
- Rather than using a constraint solver, balance in the randomization is achieved by interacting with the functional coverage model, resulting in fewer cycles;
- The initial randomization is refined by using procedural code which can easily mix directed, algorithmic, file-based methods and additional randomization; and
- A straightforward usage model, ensuring users are able to get up to speed quickly while retaining the freedom and flexibility to continue using VHDL.
Aldec tools offer the advanced randomization and functional coverage capabilities provided by OS-VVM with a simple flip of the VHDL-2008 switch; i.e. no additional licenses are required. SynthWorks, the maintainer of the OS-VVM packages, offers in-depth training for OS-VVM and supplements with additional packages for creating scoreboards, memories, and abstracting interfaces. To download the free OS-VVM packages and view additional resources, including a white paper, user guide, sample designs, and VHDL package source files please click here.
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
SynthWorks provides training in leading-edge VHDL verification techniques, including transaction-based testing, bus functional modeling, self-checking, data structures (linked-lists, scoreboards, memories), directed, algorithmic, constrained random, and coverage-driven random testing, and functional coverage. For more information, visit www.synthworks.com.
Aldec is a trademark of Aldec, Inc. SynthWorks is a servicemark of SynthWorks Design Inc. All other trademarks, servicemarks, or registered trademarks are property of their respective owners.