Cadence was cited for helping implement an interposer test vehicle using Cadence standard 3D-IC solutions that employed through-silicon vias (TSV). The project involved a system-on-chip (SoC) and eDRAM integrated on a silicon interposer.
"Our in-depth collaborations with TSMC across many advanced projects in the IC domains had enabled TSMC and Cadence to take the leadership in 3D-IC," said Dr. Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. "With the complexity levels faced by today's chip design to deliver features along with performance, power and form factor goals, new approaches are needed to stay competitive, and 3D-IC is an important industry direction for addressing those challenges. We appreciate the recognition from TSMC and look forward to enabling the semiconductor industry with this important new technology."
"We are pleased to recognize the contributions Cadence has made in the field of 3D-IC," said Suk Lee, TSMC Director of Design Infrastructure Marketing. "The deployment of these new technologies will continue to drive the expansion of computing power and performance."
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