CHAPTER 7

A 16-bit D/A interface with Sinc approximated semidigital reconstruction filter


Prev TOC Next

7.9. Interpolative D/A converter with Sinc approximation in the time domain

The signal reconstruction can be improved by using another approach based on Sinc approximation in the time domain. In this approach a reduction of power in the digital domain by a factor two can be achieved. The price paid is an increase of the filter complexity by doubling the number of current sources and shift registers with the benefit of keeping the same power consumption in the analog part. To understand the principle of the interpolative D/A converter consider first the signal reconstruction from its samples.

7.9.1 Signal reconstruction

Assume y(t) to be an ideal sampled signal. This signal can be obtained by multiplying a continuous signal x(t) with a periodic train of Dirac pulses.

(7.49)

In conformity with sampling theorem ( WKS theorem) [15] if the signal is ideally low-pass filtered, the signal can be recovered from its samples. Denote fs=1/T the sample frequency and l(t) the impulse response of an ideal low pass filter. The original function can be obtained by adding together an infinite number of Sinc pulses weighted with the sample value:

(7.50)

In fig.7.28 the reconstruction process is graphically shown. The dotted line is the sum of the Sinc functions. As long as we can generate the complete sequence of Sinc functions, the reconstruction process is ideal. In our case, the reconstruction process starts with a D/A converter which is followed by a sample-and-hold circuit and finally an analog filter. This means that the analog value coming from the D/A converter is hold until the next sample arrives. Therefore, the reconstruction of the signal is done by summing the top-flat pulses as a coarse approximation of the Sinc functions. A better approximation of the Sinc function is shown in fig.7.29.

 

Fig.7.28: Signal reconstruction

Fig.7.29: Sinc approximation

The sampling period is halved and a new pulse is present at -T/2 with a duration of T. Theoretically, dividing further the sampling interval in equal time slots and introducing new top flat pulses, the precision of this approximation can be improved. However, the complexity required to realize the filter limits the number of top-flat pulses used for this approximation.

Fig.7.30 illustrates the implementation of the Sinc approximation in time domain of fig.7.29. The number of the shift registers has been doubled and the number of the coefficients is doubled. Every coefficient is halved and repeated twice in the FIR filter. In this method, a third interpolating sample is present between two adjacent samples, equal to the arithmetic mean of the two initial samples. By doubling the number of coefficients and shift registers at the input of the analog low-pass continuous time filter, the equivalent sample frequency is doubled. Consequently, the sampling frequency of the digital filter can be reduced with a factor two without changing the sample frequency at the output of the FIR filter. The consequence is that the digital filter and the noise shaper can have a sampling frequency with a factor to lower and therefore, the power in the digital side is reduced a factor two. By halving the coefficients and repeating them twice, the complexity in the analog part increases but, the power consumption remains the same. Only the slew behavior of the opamp will limit the method. The digital part consisting of digital filters, noise shaper, clock generation circuitry can work at half of the initial clock frequency.

< href='/book//phdThesis/Image1634.gif' title='Click to enlarge this image' target='_blank'>

Fig.7.30: Interpolative D/A converter

This gives a reduction in power with a factor two. If we increase the complexity of the FIR filter with another factor two, we end up with 100 coefficients, complexity comparable with standard methods like Remez exchange algorithm. The benefit will be the reduction of power with a factor 4 in the digital domain.

Rand3D

SolidCAM: SolidCAM Dec 2017 Campaign Save 28 percent

Featured Video
Jobs
Mechanical Design Engineer 3 for KLA-Tencor at Milpitas, CA
Sr Mechanical Design Engineer for Medtronic at mounds view, MN
Senior Mechanical Engineer for BAE Systems Intelligence & Security at Arlington, VA
Urban Designer - Urban Design/Planning for SERA Architects, Inc at Portland, OR
Geospatial Systems Administrator for BAE Systems Intelligence & Security at arnold, MO
Upcoming Events
ESPRIT World 2018 at Indianapolis Marriott Downtown 350 West Maryland Street Indianapolis IN - Jun 11 - 15, 2018
HxGN LIVE 2018 at The Venetian Las Vegas NV - Jun 12 - 15, 2018
IMTS2018 International Manufacturing Tech Show at McCormick Place Chicago IL - Sep 10 - 15, 2018
Kenesto: 30 day trial



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise