Gm-C integrators for low-power and low voltage applications. A gaussian polyphase filter for mobile transceivers in 0.35

Prev TOC Next

4.3. Low voltage current Gm-C integrator with high power efficiency

The starting point for this section is the integrator shown in fig.4.9 (see also [11], [12]) which is a modified version of the integrator from reference [13]. The reason for using this integrator consists in the low-voltage, high linearity and very high frequency of operation with a high power efficiency. It is compatible with standard digital technology has a high quality factor Q and can work down to 1.5V power supply voltage. For an ideal integrator, the input differential current should flow entirely in the integration capacitance Ci. Without any compensation technique, there is always a current flowing in transistors M1 and M2 damping the integrator. Transistors M3 and M4 provide positive feedback compensation for the signal currents flowing in M1 and M2 enhancing the input resistance of the integrator. Theoretically, if matching is assumed, the gain can become infinity when compensation is achieved. The same circuit provides common-mode rejection in an efficient way. Positive feedback is a promising technique for enhancing gain in sub-micron CMOS because current matching in modern technologies improves. Denote gm the transconductance of the output transistor. The differential gain of this integrator is:



Fig.4.9: Continuous time, current, Gm-C integrator

Fig.4.10: Frequency transfer of the integrator

When a and b are equal, the differential gain becomes infinity. However, the gain is limited to some 50-60dB due to second order effects. Obviously, there are no parasitic poles in the structure and only one zero due to gate drain overlap capacitance of the NMOST transistors. The structure can be tuned by changing the value of the bias current I0. The quality factor of the integrator depends on the position of parasitic poles and zeros and also on the differential gain at DC. In our situation there are no parasitic poles and the position of the zero is at much higher frequencies compared to GBW as illustrated in fig.4.10.

The quality factor of the integrator depends on the low frequency gain of the integrator and the position of the zero:


Accordingly, the quality factor of this integrator can be as high as 100 for normal values of gain. For high-frequency and/or high Q filters it is very important to have large quality factor integrators. In a ladder filter every integrator simulates a reactive element. Then, finite gain means a lossy inductor or a lossy capacitor. For a reactance two-port with a uniform distribution of quality factors in all reactances the losses can be approximated by:


For narrow-bands, where w t gr can have values as large as 100 or more, the passband deviation is high when the Q factor of the reactances is low. The Q tuning is difficult to achieve for high Q filters. It is important to have by design a high Q integrator in order to simplify the tuning circuit or to eliminate it if possible.

4.3.1. Dynamic range and power

Assume a ratio of Ö 3 in transconductance between the NMOS and PMOS transistors and denote gm the transconductance of a transistor biased at a current level I0 having the same drive voltage as the chain M1…M3. The power spectral density of the current noise at the input is:


Consider a unity feedback configuration of this integrator. After integration we get the total output noise which can be obtained using the effective noise bandwidth approximation:


Now, we can compute the DR knowing the class A operation of the integrator and the necessity to have a modulation index mi of the current signal less than 1 in order to reduce distortions.


DR can be increased when using large capacitors at the expense of a larger passive area. From another point of view, DR is limited by the supply and modulation index mi. At low voltages we have to scale up capacitors with VDD2 in order to keep the same DR. In order to keep the same time constants in the filter and the same speed gm/Ci the currents have to scale up and power has to increase to keep the same DR. The DR*GBW of the integrator is found to be:


Hence, the minimal power needed to bias this integrator in a unity gain configuration is found at limit when VDD is larger than DP+VT.


The current efficiency of the OTA is lower than the efficiency of the current Gm-C integrator due to the need for biasing the common-mode circuit and the extra current needed to bias the output branch. Now, we can compare the minimal power of the current-mode Gm-C integrator with the minimal power of the OTA-C integrator when the DR*GBW for the two approaches is the same.


Given the values of the modulation index mi=0.8 the values a=b=1, VDD=3V, n=1.1, h OTA-C/h Gm-C=0.1 and the noise excess factor NEF=6 this yields a factor 3 in power in the favor of current Gm-C integrator.

4.3.2. The linearity of the integrator. Linearity improvement.

Consider the mobility reduction in the current term without taking into account the term dependent on VDS. The drain current of a MOS transistor can be approximated as:


In fig.4.11, a linearized integrator is being shown. Without linearization transistors M13 and M14 and the voltage dividers R1...R4, the integration principle can be explained in the following way. The input differential current is being converted into a voltage at the gates of the transistors M1...M5 and M2...M6. At the input the impedance level is low but because of the positive feedback ensured by the transistors M3 and M4 the impedance level increases. The input differential current is being forced in the integration capacitors and the output resistance of the input current sources. Theoretically, if a=b, the gain of the integrator is infinity and the current to voltage conversion undistorted. The only possible distortion term comes from the voltage to current conversion performed at the output by the transistors M5 and M6. The large signal voltages on the integration capacitors are VGS0-Vi and VGS0+Vi respectively. Denote iOD the output differential current. Without compensation we have a third order distortion term and no second order terms due to the differential symmetry:


By dividing the gate source voltages by a 1 and amplifying the current in the compensation transistors by a 2, one can find a condition for undistorted transfer in

Fig.4.11: Linearized integrator

terms of a 1 and a 2. The voltage division by a 1 is performed by the polysilicon resistor dividers R1, R2 and R3, R4. The current amplification by a 2 is performed at the output by the transistors M13 and M14. Now we can write the output currents i1,1 , i1,2 , i2,1 , i2,2 as a function of the effective gate-source voltages:





At the output, the differential current can be written as a function of the individual output currents:


By substituting (4.22) in (4.23) and under the extra condition a 2* a 13=1 the output differential current becomes:


As a conclusion, by choosing a 2 and a 1 such that a 2* a 13=1 we have a linear relationship between the output current and the input differential voltage 2Vi. However, in practical situations mismatches between the two differential branches will give extra even distortion terms.

The advantage of the method consists in the possibility of choosing different values for a 2 and a 1 and the dependence of a 2 and a 1 on ratios. Given the fact that a 2 is close to one, than a 1 will be larger than one. Another advantage would be that all VDS voltages of the transistors will be about the same and therefore, one can show that any additional term dependent on VDS in eq. (4.24) will cancel out.

SolidCAM - Learn More

Featured Video
Modeling and Simulation / HWIL Engineer for Lockheed Martin at Orlando, Florida
QA Engineer- F-35 Quality Engineering for Lockheed Martin at Forth Worth, Texas
Geologist for U. S. Dept. of the Interior at Marsing, Idaho
Geographic Information System Specialist for U. S. Dept. of the Interior at Washington, District Of Columbia
Engineer A, B or C (Transportation) for City of Austin at Austin, Texas
Project Manager, Architect, for K2M Design at Indianapolis, Indiana
Upcoming Events
EMO Hannover 2019 at Hannover Germany - Sep 16 - 21, 2019
WESTEC 2019 at Long Beach Convention & Entertainment Center 300 East Ocean Boulevard Long Beach CA - Sep 24 - 26, 2019
Engineer 3D! at Potawatomi Hotel and Casino 1721 W Canal St, Milwaukee, WI 53233 Milwaukee, WI WI - Oct 2 - 3, 2019
3D Collaboration & Interoperability Congress - 2019 at American Mountaineering Center Golden CO - Oct 8 - 10, 2019
Kenesto: 30 day trial

Internet Business Systems © 2019 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise